Chip-Package Co-Analysis and Design for SI/PI Issues of High-Speed Memory I/O Interfaces

本文針對高速記憶體中符合載線串聯終止邏輯電路(stub series terminated logic, SSTL)架構下的輸入/輸出電路(input/output circuits, I/O circuits)，在同時考慮系統信號完整性(signal integrity, SI)與電源完整性(power integrity, PI)的表現下，提出一種結合晶片—封裝結構的共模擬分析與設計方式。基於電路在暫態切換時的電流特性，本文提出三個用於評估高速記憶體電路封裝結構在信號完整性及電源完整性表現的設計參數。簡化的晶片與封裝結構分別被設計實做並進行量測，並與共模擬資料比較以驗證上述之想法。為了使動態記憶體(dynamic random access memory ,DRAM)設計者能讓電路達到更好的表現，在此將分析與設計的方法有系統的整理為一套設計流程。理論實用的部分則依照此設計流程來改善商業用DDR3記憶體模組之封裝結構。在相同佈局面積的限制條件下，原本總體表現最糟的電路組在輸入信號資料傳輸速率為5Gb/s下於輸出信號的眼高及電源端之電壓擾動分別有16.1%與10.1%的改善。To obtain better performance in signal integrity (SI) and power integrity (PI) of high-speed memory circuits, the co-analysis and design of chip-package structures under stub series terminated logic (SSTL) topology are demonstrated. Based on the characteristic current flow, three package design parameters: Ldiff, LPDN, and Lloop, are proposed to evaluate the PI and SI performance of high-speed memory input/output (I/O) circuits. The chip-package co-simulation and measurement at time-domain have reached a good agreement in both PI part and SI part to verify the ideas. A systematic design flow is constructed for dynamic random access memory (DRAM) designers to obtain better SI and PI performance. Under the design flow, an application study to improve a commercial DDR3 package, which refines from a real package substrate, is presented to have better performance in SI and PI under the condition of identical layout area. The eye-height of output signal and voltage variation of the worst case have been improved 16.1% and 10.1% at data-rate 5 Gb/s, respectively