Signal Integrity Analysis and Equalizer Design for High-Speed Interconnects in Industrial Personal Computer Mother Board

在工業電腦的多層印刷電路板當中，常見許多不連續結構，例如：連通柱與焊墊。隨著資料傳輸速率達到Gbit/s 以上時，這些不連續結構對於信號完整度的影響就必須要被考慮。 為了改善高速訊號完整度於傳輸通道眼圖的電性表現，本論文在差模連通柱殘段的末端使用電阻與電感組成的等化器，並提出一套完整的設計流程來加以設計。並且利用模擬軟體與量測散射參數，就眼圖結果來驗證此方法的正確性。為了減少反射雜訊，本論文使用在焊墊下開槽洞與在差模連通柱使用膠囊狀清潔環的補償方式，來減少訊號的反射。There are many discontinuities in the industrial personal computer printed circuit board, such as the via and pad. As the transmission data rate exceeds several Gbit/s, the discontinuities have the serious impact on the signal integrity. To improve the signal integrity on the eye-diagram performance of high-speed channel interconnection, this thesis used the resistor and inductor attached at the via stubs as an equalizer and proposed a design flow, accordingly. The design flow was verified between the simulation tools, scattering parameters, and eye measurements. To reduce the reflection noise, this thesis used the defected ground under the pad and the differential vias with the capsule-shaped anti-pad