CMOS-MEMS Testkey for Wafer-Level Mechanical Properties Extracting

本研究研發出一套適用於晶圓級檢測(wafer level testing)的材料機械性質量測技術。研究中發展一套以電信號與白光干涉儀( White Light Interferometers )檢測結果，萃取薄膜材料性質的演算法。本研究先以尤拉樑(Euler’s beam)模型以及最小能量法(minimum energy method)為理論基礎，推導出具初始應力之微橋狀樑在承受靜電負載下的吸附電壓(pull-in voltage)的近似解析解(approximate analytical solution)，藉由量測兩組長度不同的橋狀樑測試鍵(bridge-type testkey)之吸附電壓，反算其楊氏模數(Young’s modulus)與平均應力(mean stress)；再利用樑之撓曲公式(flexure formula)與彈性曲線方程式(elastic curve)，藉由量測懸臂樑型測試鍵(cantilever-type testkey)因應力釋放之自由端最大變形量，進而求得梯度應力(gradient stress)。研究中以台積電0.18 微米製程之metal 2作為測試結構材料，及參考Osterberg發表之文獻中提供的(100)單晶矽橋狀樑、(110)單晶矽橋狀樑之吸附電壓實驗值，使用本研究提出的演算法進行材料參數萃取，所得之楊氏模數、平均應力與梯度應力數值均具有良好的準確度。此外，本研究並探討此演算法之穩健性(robustness)影響因素包含吸附電壓量測之靈敏性分析(sensitivity analysis)與測試鍵尺寸效應(dimension effects)，以提供元件設計者作為設計參考指標。本研究建立之晶圓級薄膜機械性質萃取技術，可利用現有之半導體製程中使用的量測設備，於晶圓製程線上進行量測與監控。This research develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, mean stress, and gradient stress, through the external electrical circuit behavior and pre-deformation of the micro test-key. First, an approximate analytical solution for the pull-in voltages of bridge-type testkey subjected to electrostatic loads and initial stress is derived based on the Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. Second, according to the flexure formula and elastic curve of a cantilever beam, the gradient stress can be obtained by measuring the pre-deformation of the cantilever-type testkey utilizing White Light Interferometer. The test cases include the testkeys fabricated by TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work about the pull-in voltage of single crystal silicone micro bridges. The extracting material properties calculated by the present algorithm are valid. Besides, this research study the robustness of this algorithm including sensitivity analysis for pull-in voltage measurement and dimension effects of testkeys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test is non-destructive