Low Power and High Speed 64-bit Domino Logic Adder and AC Coupled Transceiver System

本篇論文針對90nm製程，提出適合先進製程的改良式前綴式加法器，使資料運算更為同步。並使用動態骨牌邏輯實現以提升速度以及利用基板偏壓技術降低其消耗功率。此加法器在2009年3月已使用UMC 90nm製造而成，操作頻率為5.4GHz，運算延遲為185ps，消耗功率為45mW。 本篇論文亦提出了一精準的量測架構，能準確的量測加法器的運算延遲，其中包含了一個鎖相迴路(PLL)與一個延遲選擇器，鎖相迴路(PLL)為整個系統之時脈產生器，輸出訊號為5.4GHz之週期訊號，延遲選擇器被使用在輸入及輸出之間，可選擇多個不同延遲時間，藉由不同相位取得正確的輸出訊號，精確的量測其運算延遲。 另外，本篇論文亦描述了一個高速且低功率損耗電容耦合傳送接收器。這種電容耦合式傳送接收器可將NRZ的資料轉換成低振幅的脈衝波，經由傳輸線傳送後，於接收端再將此脈衝波還原成NRZ的資料。在傳送端使用互補式傳輸線為基礎的鎖相迴路來提供時脈，並使用差動的傳送器來降低雜訊。而接收端電路使用被動但低功率損耗的等化器來彌補高頻的損失，以及使用電流模式的Sense Amplifier將脈衝波回復成NRZ的資料，最後利用改良的Cherry-Hooper放大器將波形放大。 最後實際以TSMC CMOS 0.18um製程下線，使用2^15-1的PRBS來給資料，將資料透過75fF電容經由10公分的FR4傳輸線來傳輸，最大可到達6Gb/s的傳輸速度，而誤碼率小於10-12。With the continuous expansion in digital information, microprocessor plays a more important role in this world than before. In microprocessor, ALU is a key component does all the information processing. In this work, an arithmetic logic system architecture which includes a high performance adder unit and the I/O interface has been proposed.n this work, a 64-bit address generation unit designed for 5.4-GHz and with 185ps latency operation in 1.2-V UMC 90-nm technology is proposed. This adder utilizes three complex domino logics stages with lower stage logic effort and well arranged interconnect routing type and thus improving 70% cross couple capacitance. Moreover, it uses Multi-Vt method to reduce power consumption. And the testing circuit is designed to providing an efficient way to estimate the performance of the adder under different conditions is proposed here too. The adder dissipates 42mW and the core area is 200μm *900μm. low-power high-speed I/O interfaced circuit name by AC Coupled Interconnect targeting for data transmission between two operation units is proposed. The circuit uses low-swing pulse signals and the voltage mode driver to reduce power consumption. Using this receiver, 6Gb/s chip-to-chip communication is demonstrated through wire-bonded ACCI channel with 74fF coupling capacitors, across 10-cm FR4 couple microstrip lines. The chip was fabricated in TSMC 0.18-μm technology. The driver and receiver dissipate 13.5mW and it can achieve error-free operation with 6Gb/s 215-1 PRBS data over 10-cm FR4 channels.Chapter 1 1ntroduction 1.1 Motivation 1.2 Organization 3hapter 2 5ackground knowledge 5.1 Introduction to Adder 5.1.1 Conventional Adders 5.1.2 Prefix Adders 9.1.3 Summary 24.2 Background Knowledge of AC Coupled Interconnect 24.2.1 Circuit Structure and Transient Waveforms of ACCI 25.2.2 Frequency Response and Power Issue 27.2.3 Valid Range of Coupling Capacitance 30hapter 3 35ur Proposed Adder 35.1 Introduction 35.2 Architecture of our Adder (Uniform Prefix Tree Adder) 35.3 Propagate and Generate Signal Generating Stage 41.4 Carry-Merge Logic 42.4.1 Domino Logic v.s. Static CMOS Logic 43.4.2 Foot Domino Logic v.s. Footless Domino Logic 45.5 Carry-Sum Signal Generating Stage 46.6 Clock Distribution 47.6.1 Domino Logic Timing Analysis 47.6.2 Clock Tree Implementation 51.7 Layout Routing Style 54hapter 4 57ulti-Vt Technology 57.1 Introduction 57.2 Threshold Voltage and Body Effect 57.3 Delay and Power Issue 59.4 Substrate-Bias Implementation 60.5 Simulation Results 62hapter 5 64esting Circuits for Adder 64.1 Introduction 64.2 Testing Structure 65.2.1 TSPC Flip-Flop 67.2.2 Phase-Locked Loop 68.2.3 Skew Controller 71hapter 6 73CCI Implementation 73.1 Voltage-Mode Driver 73.2 Low-Swing Pulse Receiver 75.3 Limiting Amplifier 78.4 Summary 85hapter 7 87xperimental Results 87.1 Adder 87.2 AC Coupled Interconnect 91hapter 8 94onclusion 94ibliography 9