A Comprehensive Study of Bias Temperature Instability, Strain, and Memory Effects on Polycrystalline Si Thin-Film Transistors

本文係研究多晶矽薄膜電晶體之穩定性、應變及記憶體效應。首先，本文研究多晶矽薄膜電晶體的直流偏壓溫度不穩定性，並針對P型及N型多晶矽薄膜電晶體，分別研究其正偏壓及負偏壓溫度不穩定性。施加正偏壓於P型電晶體及負偏壓於N型電晶體時，因為沿著元件寬度方向的邊際電晶體之氧化層厚度較薄，在施加偏壓後有較多的載子可以藉由F-N穿隧效應被捕獲於氧化層中，因此在電晶體的次臨限區域會發生嚴重的駝峰效應。 施加負偏壓於P型電晶體時，因表面的施體缺陷造成臨限電壓往負方向移動。表面缺陷是因為電洞和矽-氫鍵結的化學反應產生。此一反應在高電場及高溫時特別顯著。施加正偏壓於N型電晶體時，因為氧化層的缺陷而造成臨限電壓往正方向移動。當施加偏壓小於20伏特時，F-N穿隧效應較重要而臨限電壓偏移隨時間增加而增加。而當施加偏壓大於25伏特時，F-P發散效應較重要，故臨限電壓偏移隨時間增加而減少。 因為多晶矽薄膜電晶體在面板的驅動電路中受到高頻的交流電壓操作，因此本文探討多晶矽薄膜電晶體之交流偏壓溫度不穩定性。當薄膜電晶體的閘極電壓瞬間由反轉或是空乏狀態切換到累積狀態時，因為通道中無法立即產生累積載子，故通道與源極和汲極的電壓差增加，並產生衝擊游離而發生嚴重的劣化。 在N型電晶體的交流偏壓操作下，晶粒邊界的能障高度變大而造成電流大幅下降。而P型電晶體在交流偏壓操作下，電流會隨時間先上升再下降。電流的上升是因為衝擊游離造成的通道長度縮短。隨著時間增加，晶粒邊界的能障高度變大而造成電流下降。此交流偏壓溫度不穩定性在短通道元件或是閘極偏壓較大時特別嚴重，此一結果證明交流偏壓將在元件特性及穩定性中有所取捨。 應變矽技術是目前CMOS業界中最常使用的技術，可大幅提升N型及P型電晶體的遷移率。但應變矽技術是否可用於多晶矽薄膜電晶體產業，仍缺乏完整的分析。本文中探討不同通道方向的拉伸應力對遷移率的關係。因為多晶矽大部分的晶粒為(111)方向，故對N型電晶體施加沿通道方向的單軸拉伸應力，電子遷移率因有效質量的減少而提高。但若施加垂直通道的單軸拉伸應力，則遷移率會降低。若施加雙軸向的拉伸應力時，因為(111)方向電子的能谷為6-fold 對稱，故有效質量不變而電子遷移率不變。應用此一結果將可進一步提高顯示器產業中薄膜電晶體的驅動能力。 目前的顯示器產業中，因為多晶矽薄膜電晶體的遷移率遠大於非晶矽薄膜電晶體，故除了在面板的畫素中當作開關使用，亦可以在面板上實踐許多不同功能的電路，例如數位類比轉換器等。在未來的面板上系統中，中央處理器、記憶體、控制器將整合在單一面板當中。在本論文中，藉由調變多晶矽薄膜電晶體中晶粒邊界能障的大小，實踐了一個非揮發性的無電容記憶體。此記憶體係使用目前多晶矽薄膜電晶體的製程製造，完全不需多餘的製程步驟，並且具有非揮發性、低讀取功率損耗等優點穩故此記憶體將有助於未來面板產業的應用。 In this dissertation, bias temperature instability, strain and memory effects have been comprehensively studied on polycrystalline silicon (poly-Si) thin-film transistors (TFTs). In Chapter 2 and Chapter 3, static NBTI and PBTI are investigated on p-channel and n-channel poly-Si TFTs. For PBTI of p-channel poly-Si TFTs and NBTI of n-channel poly-Si TFTs, a subthreshold hump is induced after sufficient stress. The hump is attributed to the edge transistor along channel width direction, and is independent of nominal channel width. Carriers are injected into insulator via Fowler-Nordheim (F-N) tunneling, leading to the threshold voltage shifts. Higher electric field at edges yields more trapped electrons to create the hump. For NBTI of p-channel poly-Si TFTs, the negative threshold voltage is mainly attributed to the generation of donor type interface traps. The electrochemical reaction is driven by vertical electric field, and is facilitated at elevated temperature. For PBTI of n-channel poly-Si TFTs, positive VT shift is attributed to electron trapping in gate insulator. For VG smaller than 20 V, F-N tunneling is dominant and VT shift increases with stress time. For VG larger than 25 V, Frenkel-Poole emission is dominant and VT shift decreases with stress time. Since poly-Si TFTs in the driver circuits are subjected to high frequency voltage pulses in the practical applications. Therefore, it is of great importance to investigate the dynamic bias instability of both n-channel and p-channel poly-Si TFTs. Impact ionization is induced by lateral electric field when VG switches from inversion or depletion to accumulation bias due to the slow formation of accumulation region. For n-channel poly-Si TFTs, since grain boundary barrier height increases, drain current degrades significantly after stress. For p-channel poly-Si TFTs, drain current increases with time, then, decreases with time for long-term stress. The initial current increase is attributed to decrease of effective channel length. As stress time increases, the grain boundary barrier height increases to degrade the drain current. Noticeably, short channel devices suffer more degradation, implying a tradeoff between performance and reliability. Strained-Si technology has been extensively used in CMOS industry to enhance carrier mobility. However, the strain effect of poly-Si has not been reported yet. In this dissertation, external mechanical tensile strain is applied to n-channel poly-Si TFTs to investigate the drain current variation. Drive current enhances +5.7% but degrades -4.4% for longitudinal strain and transverse strain, respectively. The poly-Si film is mainly composed of (111)-oriented grains, measured by transmission electron diffraction pattern and powder x-ray diffraction. In addition, no obvious current change is observed for biaxial tensile strain due to the 6-fold symmetry of electron valleys of (111)-oriented Si. Improvement of poly-Si TFT performance is essential in order to achieve value-added displays where various functional circuits are integrated on the substrate. The integration level is proceeding from simple digital circuits to digital circuits such as digital-analog converters (DACs) and DC-DC converters. For the future system-on-panel (SOP) integrations, CPU, memory, and controller are combined into a single high-quality display. In the last part of the dissertation, a long data retention memory is realized by filling/emptying grain boundary traps of n-channel poly-Si TFTs. The fabrication process of the memory cell does not require additional processes, which is highly promising for future system-on-panel applications.List of Tables Vist of Figures VIhapter 1 Introduction 1.1 Motivation 1.2 Organization of the Dissertation 5hapter 2 Static Bias Temperature Instability of -channel Poly-Si Thin-Film Transistors 8.1 Introduction 8.2 Experiment Setup 10.2.1 Fabrication Process 10.2.2 Experiments of Bias Temperature Instability 13.3 Negative Bias Temperature Instability of p-channel Poly-Si TFTs 14.3.1 Introduction of Negative Bias Temperature Instability 14.3.2 Theoretical Power Law Exponent 16.3.3 NBTI of p-channel Poly-Si TFTs 20.4 Positive Bias Temperature Instability of p-channel Poly-Si TFTs 28.4.1 Motivation 28.4.2 Stress-induced Hump Effects 29.4.3 Process Optimization to Suppress Hump Effect 34.4.4 Temperature Dependence of Hump Effect 36.5 Summary 42hapter 3 Static Bias Temperature Instability of -channel Poly-Si Thin-Film Transistors 44.1 Introduction 44.2 Experiment Setup 46.3 Negative Bias Temperature Instability of n-channel Poly-Si TFTs 47.3.1 Polarity Change of Voltage Shifts 47.3.2 Negative Voltage Shift Due to Hole Trapping 49.3.3 Positive Voltage Shift Due to Interface Traps 52.4 Positive Bias Temperature Instability of n-channel Poly-Si TFTs 55.4.1 Time Dependence of Voltage Shifts 56.4.2 Temperature Dependence of Threshold Voltage Shifts 59.5 Summary 61hapter 4 Dynamic Bias Temperature Instability of oly-Si Thin-Film Transistors 63.1 Introduction 63.2 Experiment Setup 65.3 Dynamic Bias Instability of n-channel Poly-Si TFTs 68.3.1 Device Degradation Induced by Impact Ionization 68.3.2 Transient Simulation 73.4 Dynamic Bias Instability of p-channel Poly-Si TFTs 79.4.1 Device Mechanisms of p-channel Poly-Si TFTs 79.4.2 Extraction of S/D Extension Region 89.5 Dependence on Frequency and Transient Time 93.6 Threshold Voltage Shifts 96.7 Summary 100hapter 5 Mechanical Strain Effect of n-channeloly-Si Thin-Film Transistors 101.1 Introduction 101.2 Fundamentals of Strained-Si Technologies 103.2.1 Substrate Strain 104.2.2 Process Strain 105.2.3 Mechanical Strain 107.3 Mechanical Strain Effect of n-channel Poly-Si TFTs 107.3.1 Experiment Setup 107.3.2 Mechanical Strain of n-channel Poly-Si TFTs 111.3.3 Composition of Poly-Si Film 114.3.4 Mechanisms of Mobility Variations 119.4 Summary 121hapter 6 Long Data Retention 1T Memory Cells y n-channel Poly-Si TFTs 122.1 Introduction 122.2 Experiment Setup 125.3 1T Channel Trap Memory Cells 126.3.1 Operation Principles of 1T Channel Trap Memory Cells 126.3.2 Retention and Endurance Characteristics 134.3.3 Process Variation 136.3.4 Optimization of Operation Voltages 138.4 Summary 140hapter 7 Conclusion and Future Work 142.1 Conclusion 142.2 Future Work 145eference 14