Design and Implementation of Fully-Differential Comparator-Based Switched-Capacitor Analog-to-Digital Converters

近期的研究文獻發表了一種以比較器作為基礎架構的切換電容式(CBSC)電路，以去除在傳統實現方法中必須使用到的運算放大器。此架構的基本觀念為利用一個具有偵測虛接地臨界點能力的比較器來取代迫使虛接地形成的運算放大器。這個電路的原始雛型是以單端式的管線化類比數位轉換器來實現，然而對於現今的混合訊號積體電路而言，為了具有對供應電壓變異以及電路基板雜訊的良好抵抗能力，全差動式的電路架構是不可或缺的。 為了解決這個問題，這篇論文提出了一個以比較器作為基礎架構的全差動切換電容式電路，並將其實現於一個每秒兩百五十六萬次取樣的二階三角積分調變器，以及一個可操作在每秒兩千次到一千萬次取樣且功率可隨取樣頻率自我調整的管線化類比數位轉換器。藉由所提出的全差動CBSC積分器以及其共模回授電路，當此三角積分調變器操作在六十四倍的超取樣比時，在兩萬赫茲的信號頻寬內可達到65.3dB的訊號對雜訊加失真比(SNDR)以及71dB的輸入動態範圍。此三角積分調變器的有效面積為0.21平方毫米，而當供應電壓為1.8伏特時，其功率消耗為0.42毫瓦特。 為了實現一個功率可隨取樣頻率自我調整的全差動CBSC管線化類比數位轉換器，這篇論文提出了一個使這個架構能夠自動調整電流強度的方法，以確保當取樣頻率下降時其線性度和SNDR能有效的提升。實驗的結果證明了當操作在每秒一千萬次取樣時，此類比數位轉換器可達到53.3dB的SNDR和62.3dB的無雜訊動態範圍(SFDR)，且其功率消耗在1.8伏特的供應電壓下為1.95毫瓦特。此外，當取樣頻率逐漸由每秒一千萬次降低到每秒兩千次時，此類比數位轉換器在自動調整電流機制開啟下的SNDR亦會由53.3dB逐漸上升到最高為56.6dB，比起當自動調整電流機制關閉時皆高了2-3dB。最後，隨著取樣頻率逐漸地下降，此類比數位轉換器的功率消耗可從1.95毫瓦特(每秒一千萬次取樣)持續降至131.5微瓦特(每秒兩千次取樣)，證明了其功率隨取樣頻率自我調整的功能。A comparator-based switched-capacitor (CBSC) circuit topology published recently was introduced to substitute conventional op-amp-based designs in pipelined ADCs. The general concept of CBSC technique is to replace an op-amp with a threshold-detection comparator which is able to detect virtual ground condition rather than forcing it. The original CBSC prototype is realized with a singled-ended pipelined ADC. Nevertheless, for better rejection of supply and substrate noise, fully-differential circuit architecture is indispensable in modern mixed-signal integrated circuits where the di/dt noise from the digital circuits may be a severe problem to the analog parts on the same chip.o address the above issue, fully-differential comparator-based switched- capacitor (CBSC) circuits are proposed in this thesis. A 2.56MS/s second-order delta-sigma (ΔΣ) and a 10MS/s to 2kS/s power-scalable 10-bit pipelined ADC with self-adjusted current scaling have been realized with the presented techniques. By using the proposed fully-differential CBSC integrators and common-mode feedback circuits, the prototype second-order ΣΔ modulator achieves 65.3dB SNDR and an input dynamic range of 71dB within the signal bandwidth of 20 kHz, which corresponds to an oversampling ratio of 64. The active area of the ΣΔ modulator is 0.21mm2, while the power consumption excluding output buffers is 0.42mW at 1.8V.o realize the power-scalable CBSC pipelined ADC, a self-adjusted current scaling (SACS) method is presented to enhance linearity and SNDR when decreasing the sampling rate. Experimental results show that the ADC achieves 53.3dB SNDR and 62.3dB SFDR while sampled at 10MS/s and consuming 1.95mW from a 1.8V supply, which obtains a figure-of-merit (FOM) of 510fJ/step. In addition, when the sampling rate gradually reduces from 10MS/s to 2kS/s, the peak SNDR increases from 53.3dB to 56.6dB at most, and is constantly 2-3dB higher than the situation when SACS is disabled. Finally, the power consumption as the operating frequency goes down continuously decreases from 1.95mW (10MS/s) to 131.5μW (2kS/s), validating the power scalability of the prototype ADC.Table of Contentsbstract ………………………………………………………………iable of Contents ……………………………………………………vist of Figures ………………………………………………………ixist of Tables ………………………………………………………xivhapter 1ntroduction……………………………………………………………1.1 Motivation…………………………………………………………1.2 Thesis Organization ……………………………………………2hapter 2 undamentals of Analog-to-Digital Converters……………………3.1 Introduction………………………………………………………3.2 ADC Performance Metrics………………………………………5.2.1 Resolution ………………………………………………………5.2.2 Signal-to-Noise Ratio (SNR)…………………………………6.2.3 Signal-to-Noise-plus-Distortion Ratio (SNDR)………………8.2.4 Effective Number of Bits (ENOB)……………………………8.2.5 Dynamic Range…………………………………………………9.2.6 DNL and INL ……………………………………………………10.3 Pipelined ADC Basics……………………………………………12.3.1 Fundamentals of Pipelined ADCs……………………………12.3.2 1.5-Bit/Stage Architecture……………………………………13.4 Delta-Sigma ADC Basics………………………………………15.4.1 Fundamentals of Delta-Sigma Architecture…………………15.4.2 Noise Shaping …………………………………………………16hapter 3 ully-Differential Comparator-Based Switched-Capacitor (CBSC) Circuits……19.1 Basic Principles of Operation of CBSC Circuits………193.1.1 Op-Amp Based Switched-Capacitor Gain Stage……193.1.2 Comparator-Based Switched-Capacitor Gain Stage…21.2 Practical Charge Transfer Phase in CBSC Circuits……223.2.1 Preset Phase………………………………………………223.2.2 Coarse Charge Transfer Phase…………………………233.2.3 Fine Charge Transfer Phase……………………………24.3 Fully Differential CBSC Circuits…………………………263.3.1 Fully-Differential CBSC Gain Stage……………………263.3.2 Charge Transfer in Fully-Differential CBSC Gain Stage……27hapter 4 ully-Differential CBSC 2nd-Order Delta-Sigma Modulator…31.1 System Architecture ………………………………………314.1.1 Linear Model of 2nd-Order ΔΣ Modulator………………314.1.2 Signal Scaling……………………………………………34.2 Circuit Architecture…………………………………………364.2.1 CBSC Integrator …………………………………………364.2.2 Fully-Differential CBSC 2nd-Order ΔΣ Modulator……374.2.3 Threshold-Detection Comparator………………………404.2.4 Ramp Generator…………………………………………414.2.5 Common-Mode Feedback Circuit………………………424.2.6 1-Bit Quantizer …………………………………………444.2.7 Nonoverlapping Clock Generator………………………45.3 Performance Limitation……………………………………46.4 Simulation Results and Layout …………………………494.4.1 Pre-Layout Simulation Results ………………………494.4.2 Layout and Floorplan……………………………………514.4.3 Post-Layout Simulation Results………………………52.5 Test Setup and Experimental Results …………………544.5.1 Pin Assignment…………………………………………564.5.2 Input Signal Source and Input Termination Circuit…574.5.3 Power Supply and Ground ……………………………584.5.4 Reference Voltage Generator …………………………594.5.5 Measurement Results …………………………………60.5 Conclusion…………………………………………………63hapter 5 10MS/s to 2kS/s Power-Scalable Fully-Differential CBSC Pipelined ADC with Self-Adjusted Current Scaling …………………………………65.1 Concepts of Power Scaling and Current Scaling ………655.1.1 Power Scaling ……………………………………………655.1.2 Self-Adjusted Current Scaling (SACS)…………………68.2 Circuit Architecture…………………………………………71.2.1 Power-Scalable Fully-Differential CBSC Pipelined ADC with SACS ……………………………………………………………………71.2.2 Threshold-Detection Comparator………………………74.2.3 Self-Adjusted Ramp Generator…………………………77.2.4 Common-Mode Feedback Circuit………………………79.2.5 Sub-ADC …………………………………………………80.3 Performance Limitation……………………………………82.4 Simulation Results and Layout …………………………90.4.1 Pre-Layout Simulation Results ………………………90.4.2 Layout and Floorplan……………………………………91.4.3 Post-Layout Simulation Results………………………92.5 Test Setup and Experimental Results …………………94.5.1 Test Setup………………………………………………94.5.2 Pin Assignment…………………………………………96.5.3 Measurement Results …………………………………97.6 Conclusion ………………………………………………104hapter 6 onclusion………………………………………………………107.1 Conclusions…………………………………………………107.2 Recommended Future Work………………………………108ibliography………………………………………………………10