A Self-Testable Delta-Sigma Modulator for Built-on-Scribe-Line TFT LCD Source Driver Testing

在本論文中，我們針對液晶顯示器驅動IC，提出一個低成本、晶圓層級的測試方法；這方法是將測試電路實現在晶圓切割線上。針對原本所需的自動化測試設備，我們提出的方法不僅大幅減少所需要的輸入輸出通道，並且可以捨棄高速數位化設備的需求。在測試電路裡，我們選擇一階三角積分調變器當作數位化設備，用來量化驅動IC 的輸出電壓。這個三角積分調變器可以容忍相對較高的製程變異以及尺寸匹配的不精確，對於我們的測試電路，三角積分調變器將是類比數位轉換器的最佳選擇。 為了確保這個三角積分調變器的可靠度，我們也提出一個低成本，並且極有效益的可測試設計技術，去診斷三角積分調變器中的積分器漏電流現象。所提出的方法是一個低成本的解決方案，因為它只需要在原本的三角積分調變器外，添加兩個額外的多工器，其次只需要一個直流電壓當作它的測試源，並且經由調變後的數位位元串流，即可簡易的分析出積分器漏電流現象。這個提出的測試方法也可以應用到其他三角積分調變器架構，例如更高階的三角積分調變器，以及多級串接三角積分調變器。模擬結果顯示，即使加入雜訊考量，對於積分器漏電流仍有極為精確的評估結果。In this thesis, we present a low-cost wafer-level test methodology for the source driver ICs of liquid crystal displays; the idea is to realize the test circuitry on the wafer scribe line. The proposed technique not only substantially reduces the required ATE I/O channels but also eliminates the need of high-speed digitization units on the ATE. In this test circuitry, a first-order ΔΣ modulator is chosen as the digitizer to quantize the driver output voltage. The ΔΣ modulator can tolerate relatively high process variations and matching inaccuracy, which is the best candidate of A/D converter in our test circuit design. To ensure the reliability of the digitizer, a low-cost and efficient Design-for-Test(DfT) technique is also developed to characterize the integrator leakage of ΔΣ modulator. The proposed technique is a low-cost solution because it only adds two multiplexers to the modulator, utilizes DC voltage as the test stimulus, and estimates the integrator leakage by analyzing the digitized bit stream. This proposed method can also be applied to other ΔΣ modulator structures, e.q., higher-order and MASHtructures. Simulation results show that accurate estimations of the integrator leakage can be achieved even at the presence of noise.誌謝...................................................... I文摘要................................................. IIbstract................................................ IIIable of Contents........................................ IVist of Figures.......................................... VIist of Tables......................................... VIIIhapter 1 Introduction.................................... 1.1. Motivation........................................... 1.2. Contribution......................................... 3.3. Thesis Organization.................................. 4hapter 2 Preliminaries................................... 5.1. TFT-LCD Source Driver................................ 5.1.1. Source Driver Architecture......................... 5.1.2. Source Driver DAC Specification.................... 6.2. Basic Concept of ΔΣ Modulator...................... 7.2.1. Introduction to ΔΣ Modulator..................... 7.2.2. Quantization Noise................................. 7.2.3. Oversampling Technique............................ 10.2.4. Noise-Shaped ΔΣ Modulator....................... 12.2.5. The Single-Bit First-Order ΔΣ Modulator......... 14.2.6. The Effect of Integrator Leakage.................. 15.2.7. The Related Work for ΔΣ Modulator Testing....... 16hapter 3 The ΔΣ Modulator ADC for Built-On Scribe Lineource Driver Testing ................................... 18.1 Overview of the LCD Source Driver IC Testing......... 18.2 Proposed Source Driver Test Technique................ 19.2.1 Design Consideration .............................. 19.2.2 The Architecture of Built-On Scribe Line Testing... 21.2.3 Test Flow ......................................... 22.3 Test Circuitry Implementation ....................... 24.3.1 Channel Selection Logic ........................... 24.3.2 The Proposed Low-Cost Digitizer — An Adaptive ΔΣ Modulator ADC............................................ 25.4 Integration with the Source Driver IC ............... 33.5 Simulation Results .................................. 34hapter 4 The Built-In ΔΣ Modulator Leakage Testing.... 36.1 Overview of ΔΣ Modulator Testing .................. 36.2 The Architecture of DfT ΔΣ Modulator .............. 37.3 The Test Strategy ................................... 38.2.1 Phase I: Integrator Charging ...................... 39.2.2 Phase II: Integrator Discharging .................. 41.2.3 Phase III: Leakage Amplification Adjustment ....... 43.4 Behavior Simulation Results ......................... 44.3.1 Operational Amplifier and Switch Noise ............ 46.3.2 DC Test Input Noise ............................... 47.3.3 Comparator Offset ................................. 49.5 Circuit Implementation .............................. 50.5.1 Normal Mode ....................................... 51.5.2 Test Mode ......................................... 52hapter 5 Conclusion and Future Work .................... 54eference ............................................... 5