A Novel Low Cost Realization of Photonic Crystal Power/Ground Layer in PCB for Noise Suppression

為了抑制高速數位電路中的同步切換雜訊，一種可應用於印刷電路板和封裝中的光子晶體電源層的結構在先前被提出。而由於目前發展出的高介電材質本身特性，此種光子晶體電源層的結構難以實際製作於印刷電路板和封裝中。有鑑於此，本論文提出兩種結構來克服在實現光子晶體電源層時所遇到的困難。利用高介電連通柱束光子晶體結構可得到許多不同等效介電常數的等效高介電材質，利用這些等效材質在設計截止頻帶時能作更多變化，更有彈性。利用貫孔式光子晶體電源層的結構可實際在四層印刷電路板中製作光子晶體電源層的結構，而貫孔式光子晶體電源層與先前的光子晶體電源層，兩者之第一截止頻帶頻段相近。而貫孔式光子晶體電源層也實際製作於四層板FR4的印刷電路板，其模擬與量測結果相當吻合。而對於射頻電路雜訊抑制的效果，也將在此作驗證。This thesis focuses on the suppression of simultaneous switching noise (SSN) in high-speed circuits. A photonic crystal power/ground layer (PCPL) was proposed previously to eliminate the SSN in the PDN of the PCB or package. Since the PCPL structure is hard to be fabricated in PCB and package due to the property of presently developed High-DK material, two structures are proposed in this thesis to overcome the difficulty. The high-DK via bundle PCPL structure is proposed to provide several equivalent High-DK materials with different effective DK to design the bandgap more flexibly. The through hole PCPL (TH-PCPL) structure is proposed to be a low cost realization of the PCPL structure in four layer PCB. The first stopband of TH-PCPL is almost the same as the first stopband of previous PCPL. TH-PCPL is fabricated on four layer FR4 PCB and good agreement is shown between the measurement and simulation results. Demonstration of noise isolation on RF circuits is shown in the last section.第一章 簡介 1.1 研究動機 1.2 同步切換雜訊現象與成因 2.3 章節概要 4 二章 同步切換雜訊之抑制方法與比較 6.1 表面佈置去耦合電容 6.2 嵌入式去耦合電容 9.3 切割式雜訊隔離電源平面 11.4 嵌入式電磁能隙結構 13.5 共平面式電磁能隙結構 18 三章 光子晶體電源層 20.1 光子晶體能隙結構 20.2 色散圖與頻帶分析 21.3 光子晶體電源層結構 31.4 能隙分佈圖與有效頻寬設計 32.5 混合型光子晶體電源層結構 36.6 光子晶體電源層之電源完整度效能表現 39 四章 新式低成本光子晶體電源層 42.1 高介電材質與嵌入式電容 42.2 高介電連通柱束光子晶體結構 45.3 貫孔式光子晶體電源層 50.4 貫孔式光子晶體電源層之電源完整性效能表現 52.5 與射頻電路之共模擬與量測 56 五章 結論 63考文獻 6