A Priority Based Method for Output Arbiter on etwork-on-Chip Router

隨著晶片製程技術的進步，現今一個晶片上已可以容納超過一億個邏輯閘，因此晶片系統的設計將容許涵蓋數量龐大的矽智財核心，然而各個矽智財之間的訊息交換將會形成一項新的挑戰，因此近年晶片網路架構被提出，它提供一個具良好延伸性並且可靠的晶片通訊方式。二維網格拓樸架構在過去的晶片網路設計中被普遍的使用，因為它能使用簡單的路由演算法，並且具有好的網路延展性。低傳輸延遲已經成為網格晶片和傳輸架構上最重要的議題。而造成延遲的主要來源是網路的壅塞程度。在本篇論文中，我們偵測網路中是否有壅塞發生，並且使用以優先權為基礎的輸出仲裁器來消除網路壅塞。最後的實驗結果中顯示：在均勻分散式的流量測試環境下，能在網路開始達到飽和後降低20%以上的傳輸延遲。在熱點式的流量測試下，能在網路開始達到飽和後降低30%以上的傳輸延遲。最後在影像物件平面編碼器的流量測試下也能降低10%以上的傳輸延遲。在付出的額外面積成本方面，五個輸出仲裁器合起來多不到1%的面積成本。With the development of deep submicron chip technology, a chip can pack more than a billion transistors nowadays. This capacity will allow the System-on-Chip (SoC) designs with a large amount of IP cores on a single chip. However, the inter-communication between IP cores becomes a new challenge. In recent years, Network-on-Chip (NoC) has been proposed to provide an on-chip communication infrastructure with better scalability and reliability. The 2D mesh is a very popular topology of previous NoC designs, because of the simplicity with designing its routing algorithm and network scalability. The low latency design is one of the most important issues to Network-on-Chip design and the implement of scalable communication structures. The congestion delay is the most important issue of latency. In this thesis, we propose a priority based output arbitration method to eliminate the congestion states of the NoC. By detecting and dispatching the packet requirements from different directions, the packets have different priorities. According to the priorities, the packets can pass the congested router in order. Simulation results demonstrate that the proposed method can reduce the transmission latency about 20% in uniformly distributed traffic and about 30% in hot-spot traffic in saturation point when compared with the conventional router. Moreover, in VOPD traffic, the proposed method can reduce latency more than 10% when the injection rate is greater than 11 (flits/nodes/cycle). In the router design, the new arbiter area overhead is less than 1%.誌謝 I文摘要 IIBSTRACT IIIONTENTS IVIST OF FIGURES VIIST OF TABLE VIIHAPTER 1 INTRODUCTION 1.1 WHY NETWORK ON CHIP 1.2 BASIC NETWORK ON CHIP ARCHITECTURE 4.3 THESIS ORGANIZATION 5HAPTER 2 BACKGROUND 6.1 NOC TOPOLOGY 6.1.1 Mesh and Torus type topologies 6.1.2 Tree type topologies 8.1.3 Ring type topology 9.2 SWITCHING TECHNIQUES 10.2.1 Communication unit 10.2.2 Circuit switching 11.2.3 Packet switching 11.2.4 Store-and-forward 11.2.5 Cut-through 12.3 ROUTING ALGORITHM BASICS 13.3.1 Where the decision are taken 13.3.2 How a path is defined 14.3.3 The path length 14-4 VIRTUAL CHANNELS 15-5 ROUTER STRUCTURE 17HAPTER 3 PROPOSED ARBITRATION METHOD 20.1 MOTIVATION 20.2 RELATED WORK IN ARBITER DESIGN 21.2.1 Round-Robin scheduling algorithm 21.2.2 Round-Robin with least recently served scheduling algorithm 22.2.3 Round-Robin based path scheduling algorithm 23.2.4 Round-Robin based distance scheduling algorithm 24.2.5 Round-Robin based arrival and left scheduling algorithm 24.3 THE PROPOSED ARBITER ARCHITECTURE 25.3.1 Definition of dynamic priority 25.3.2 The proposed scheduling algorithm 29.3.3 Arbiter Architecture 32HAPTER 4 EXPERIMENTAL RESULTS 33.1 SIMULATION INFRASTRUCTURE 33.2 EXPERIMENTAL RESULTS 36.2.1 Area 36.2.2 Performance 37HAPTER 5 CONCLUTION 43EFERENCE 4