A GA-based Automatic Layout System for Analog IC Layout Design

隨著半導體產業的蓬勃發展，為了提升競爭力與增加收益，半導體產品的開發時程也日益緊縮。本研究旨在針對類比式電路產品開發流程中的佈局設計部分提出改善方法，期能縮短類比式電路產品開發時程。類比式電路產品而言，佈局設計對產品的最終成效影響甚大，佈局設計也是一項高度依賴設計人員的經驗與專業技巧之工作。為了提升類比式電路產品開發的整體效率，本研究提出一個類比式IC設計之自動化佈局系統，此系統以考量晶片面積利用率、電路元件之關連關係與電路元件的熱能消耗此三要素，透過系統佈置設計(SLP)流程與基因演算法之求解，以改良式樹狀結構的佈局方式，在短時間內快速提供設計人員最適合的佈局方式。研究最後以類比式電路產品為例，透過此自動化佈局系統重新進行佈局設計，並透過模擬與實際上的比較來驗證此系統。Due to the continuous breakthrough of manufacturing process and market expansions in semiconductor industry, semiconductor product development time is more and more tighten for reducing time to market, and increasing the benefits of the upstream and downstream members in the design chain. The focus of this research is the development of automatic layout system which is expected to improve the layout design procedure for analog IC product developments. bviously, layout extremely affects the performance of analog IC products, and it is truly a time-consuming work to develop an analog IC products. Moreover, the layout design procedure of analog IC highly depends on designer’s experience and expertise. In order to improve the efficiency of analog IC product development process, automatic layout system (ALS) is established in this research for providing layout design pattern quickly. Core chip area utility ratio, input/output relationship between components and the power consumption produced from thermal noise of analog circuits are concerned in automatic layout system, and layout patterns through a revised tree-structure methodology can be acquired quickly. The layout problem is solved through systematic layout planning (SLP) process flow and genetic algorithm (GA). Designers can acquire the suitable layout pattern immediately from automatic layout system.o verify this automatic layout system, two existing analog IC products are chosen as testing samples. The comparisons between actual layout and layout from automatic layout system are listed in the following content.List of Tables viist of Figures viihapter 1 Introduction 1.1 Motivation 1.2 Contributions 2.3 Thesis Organization 4hapter 2 Relevant Research and Background Knowledge 5.1 Semiconductor Manufacturing Process 5.2 Analog IC Product Development Process 9.2.1 Introduction to Analog IC Design 9.2.2 Mask, Manufacturing, Packaging, and Testing 16.3 Systematic Layout Planning 19.4 Genetic Algorithm 22.5 Taguchi Method 29hapter 3 Consideration of Analog IC Layout Design 33.1 Differences between Digital and Analog IC 33.2 Solve the Layout Problem through SLP Methodology 34.3 Layout Performance Indices 37.3.1 Chip Area 38.3.2 IO-relationship 39.3.3 Power Consumption 41hapter 4 Automatic Layout System 44.1 Data Input 44.1.1 Capacitor 45.1.2 Resistor 49.1.3 Transistor 51.1.4 Inverter 56.1.5 NAND Gate 57.1.6 Switch 59.1.7 Arrangement Units 60.2 Automatic Layout Algorithm 63.2.1 Revised Tree-Structure Methodology 63.2.2 Non-Overlapping Check 66.3 GA Algorithm 69.3.1 Computing Flow 70.3.2 Chromosomes Encoding 71.3.3 Fitness Function 72.3.4 GA Operations 73.3.5 Termination 78.4 Parameter Optimization 78.4.1 Factor Selection 79.4.2 Experimental Results 80hapter 5 Application and Case Study 83.1 RF to DC 83.1.1 Requirement of Basic Components 84.1.2 Arrangement Units and Layout Results 85.1.3 Implementation and Comparison 90.2 DC-BIAS 95.2.1 Requirement of Basic Components 95.2.2 Arrangement Units and Layout Results 99.2.3 Implementation and Comparison 103hapter 6 Conclusions and Future Works 110.1 Conclusions 110.2 Future Works 111eferences 11