Flexible and Cost Effective Transport Stream Processor for Digital TV

近幾年來，數位電視正漸漸取代傳統的類比電視。而目前的數位電視標準之中，例如歐洲規格的Digital Video Broadcasting (DVB)，美洲規格的AdvancedTelevision System Committee (ATSC)等等，都是架構在MPEG-2 System Layer之上。其中所有的數位訊號都是以MPEG-2 System Layer 所訂定的傳輸資料流做為傳輸用的格式。在數位電視的標準的規範之下，數位電視的內容提供者可以提供更多樣的服務，例如電子節目表單(Electric Program Guide)、互動電視(Interactive TV)等等。這同時也代表傳輸資料流中的資料格式也因此越來越複 雜。所以，每個數位電視接收端必備的傳輸資料流處理器，必須有能力去處理越形複雜的傳輸資料流，同時符合一般IC 設計低成本的需求。 在本篇論文中，我們提出一個彈性化的傳輸資料流處理器架構以做為數位電視系統中的矽智產設計。從我們的分析之中可以得知，一個傳輸資料流封包所需要的平均運算量遠少於實際上由規格得出的平均可用的時序數。考慮到彈性化的需求，我們提出一個以微處理器為核心的傳輸資料流處理器架構。經由有效率的軟硬體運算切分，此傳輸資料流處理器可以在低成本的需求之下達到高彈性化的目標。更進一步，我們設計一特殊指令集使微處理器可以更有效率的處理資料流 中的位元資料。此外，我們也提出一個可適用於分解位元資料群組的泛用資料分解引擎。藉由此資料分解引擎的輔助，用於分解資料群組的指令位元組數量可以大幅減少為較小長度的用於資料分解引擎的設定用位元組數量。有了這些特性，晶片中的記憶體使用量便可以大幅減少，而且只有少量增加的硬體花費。 我們所提出的傳輸資料流處理器實際上使用的邏輯閘個數大約是2 萬，而晶片上之記憶體的總使用量在基本功能的需求下為36,064 位元。經由實作的結果，此傳輸資料流處理器與其他類似的解決方案比較，可以節省大約50%的晶片面積。此外，與只有一般指令集的微處理器比較，我們設計的特殊指令集可以節省大約14.2%的晶片面積，而資料分解引擎可以節省大約6.8%的晶片面積。In recent years, a trend grows tremendously that a digital TV signal delivery system will replace the existing analog TV broadcast system. All digital TV standards are specified based on MPEG-2 system layer, such as Digital Video Broadcasting (DVB) and Advanced Television Systems Committee (ATSC), where the digital TV signals are delivered as the form of MPEG-2 transport stream. Television service providers of each country obey these standards and supply various services, such as E-learning, electrical program guide (EPG), or Interactive TV. This development also results in complicated content of transport stream. Therefore, a transport stream processor is required for every digital TV devices, and both low hardware cost and high flexibility are important requirements. In this thesis, we propose a flexible transport stream processor hardware intellectual property (IP) of digital TV System-on-a-Chip (SoC). As a result of our analysis, it can be evidenced that the average operation count needed to process a transport stream packet is much lower than the constraint which is derived from the specification. Considering of flexibility, we propose a micro-controller based architecture of transport stream processor for digital TV. Because of efficient software/hardware partitioning, the transport stream processor can achieve high flexibility with low hardware cost. Furthermore, we design a special instruction set of micro-controller for processing data fields efficiently. Additionally, a generalized parsing engine suitable for paring grouping bit-fields is also proposed. With assistance of the generalized parsing engine, the total instruction bytes executed by micro-controller for parsing fields are greatly reduced to small size of configuration bytes executed by parsing engine. With these features, the usage of on-chip memory can be reduced with small hardware overhead in this design. The gate count of the proposed transport stream processor is 20k while the size of on-chip memory is 36,064bits for baseline functions. The Implementation results show that the hybrid transport stream processor architecture can saves about 50% chip area as compared to other solutions. The special instruction set can save about 14.2% chip area while the parsing engine can save about 6.8% chip area compared with micro-controllers with only the general instruction set.Abstract ix 1 Introduction 1 1.1 The Overview of Digital TV . . . . . . . . . . . . . . . . . . . . 1 1.2 DTV Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.1 DVB DTV System . . . . . . . . . . . . . . . . . . . . . 2 1.2.2 ATSC DTV System . . . . . . . . . . . . . . . . . . . . . 3 1.3 Digital TV Receiver System . . . . . . . . . . . . . . . . . . . . 4 1.4 IC Design in Digital TV Industry . . . . . . . . . . . . . . . . . . 4 1.5 Intellectual Property and System on Chip . . . . . . . . . . . . . 6 1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Overview of The MPEG-2 system layer 9 2.1 Hierarchy of MPEG-2 Bit-stream Definitions . . . . . . . . . . . 10 2.2 Buffer of Encoders and Decoders . . . . . . . . . . . . . . . . . . 15 2.3 Synchronization between Multiple Stream Type . . . . . . . . . . 16 2.3.1 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.2 Clock Reference . . . . . . . . . . . . . . . . . . . . . . 18 2.4 Packetised Elementary Stream . . . . . . . . . . . . . . . . . . . 19 2.5 Program Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.6 Transport Stream . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.6.1 Program Specific Information . . . . . . . . . . . . . . . 23 3 Analysis of Transport Stream Processing 31 3.1 Transport Stream Processing . . . . . . . . . . . . . . . . . . . . 33 3.1.1 Basic Functions of Transport Stream Processing . . . . . 33 3.1.2 Previous Works of Transport Stream Processor . . . . . . 39 3.2 DTV System Analysis . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.1 Bandwidth Overhead of Transport Stream on System Bus 44 3.2.2 Analysis of Transport Stream Operations . . . . . . . . . 48 3.3 Analysis Conclusion . . . . . . . . . . . . . . . . . . . . . . . . 49 4 Proposed Architecture of Transport Stream Processor 51 4.1 Design Motivation . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2 Design Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3 Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.4 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . 54 4.4.1 Architecture Overview . . . . . . . . . . . . . . . . . . . 54 4.4.2 Processing Core . . . . . . . . . . . . . . . . . . . . . . 57 4.4.3 Parsing Engine . . . . . . . . . . . . . . . . . . . . . . . 66 4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5 Implementation Results and Analysis 71 5.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2 Implementation Result . . . . . . . . . . . . . . . . . . . . . . . 72 5.2.1 VLSI Chip Implementation . . . . . . . . . . . . . . . . 72 5.2.2 Reference Simulator . . . . . . . . . . . . . . . . . . . . 77 5.3 Analysis Result . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6 Conclusion 8