Modeling, Analysis, and Design for Bends and Signal Traces Crossing Slot Discontinuities of Differential Transmission Lines

當高速電腦設計的趨勢，使得印刷電路板上面元件之間的匯流排速度越來越快時，在效能的限度與需求上，將使得信號完整度(Signal Integrity)和電磁相容(Electromagnetic Compatibility)領域面臨很多新的問題。由於差模信號具備有低雜訊產生與高共模雜訊抑制的能力，因此在具有數十億位元的數位應用產品上被廣泛地使用。而使用這種設計的方式，針對整個信號連線中的差模不連續結構特性，就有被探討的需要並進而建構其適用之 模型。 在本論文中，一種針對強耦合差模傳輸線的去內嵌方法被提出，並應用來萃取等效的集總電路模型。此外，一種結合一維傳輸線模型與二維時域有限差分的方法，將有效率地被利用來處理信號與電源完整度(Power Integrity)整合的問題。對於前面所提，在信號層上的訊號完整度問題，將以差模轉角為例；而對於後者，分析信號與電源完整度整合的問題，將以差 模微帶線跨越電源或是接地層上的槽線為例。 在高速數位電路設計上，兩種常用以降低共模雜訊的差模轉角佈線結構，如背對背雙轉角與一個轉角再搭配迂迴繞線，本論文將探討與分析其於時域下的信號完整度。而一種新穎的並聯補償電容將被提出，以強化信號完整度之設計需求。另外，也透過模擬與實驗結果的一致性，驗證了轉 角等效電路模型與轉角加上補釘補償電容的可行性。 在論文中也探討了使用差模信號，來降低因爲槽線所引發的接地雜訊。一種有效率地結合二維時域有限差分法、差模信號線等效電路與槽線等效電路的方法被建立，並用以分析三層板結構的接地雜訊耦合。再者，一種用以了解爲何使用差模微帶線，能夠降低接地雜訊的簡易模型也將被提出。而影響雜訊降低的各種因素也將被探討，如耦合係數、上升時間、差模信號的時間偏移與非對稱結構的的槽線。一個呈現信號間由於槽線所引發接地雜訊的雜訊耦合實驗結構被建立，並也使用差模信號線去達到該雜訊耦合降低的效果。最後，藉由實驗與模擬結果比較的一致性，來驗證 所提出的等效模型與分析結果。While the high-speed computer design is toward increasing the bus speeds between components on a Printed Circuit Board (PCB), it faces many new problems the Signal Integrity (SI) and Electromagnetic Compatibility (EMC) issues concerned in the performance margin and requirement. In favor of the low-noise generation and high common-mode noise immunity, the differential signaling has become a popular option for multi-gigabit digital applications. To take the advantages of this design scheme, the differential discontinuities through the signaling interconnection are needed to be characterized and constructed into the feasible models accordingly. In this dissertation, a more general approach for de-embedding the strongly coupled differential transmission-line effect is thus developed to extract its lumped equivalent circuit model. Furthermore, an efficient scheme by combining the one-dimensional transmission-line model with the two-dimensional Finite-Difference Time-Domain (FDTD) analysis is extended to simulate the signal and power integrity issues. For the former part, signal integrity effects in the signal level using differential bends are chosen as an example. For the latter part, the signal propagation flowing on differential microstrip lines above a split power-ground plane serves as an example. The signal integrity analyses for bent differential transmission lines in a high-speed digital circuit are therefore performed in the time domain. Two practical compensation schemes, the dual back-to-back bends and bend with a detour, for the common-mode noise reduction are further investigated. To alleviate the common-mode noise at the receiver, a novel compensation scheme in use of the shunt capacitance is also proposed. Furthermore, the comparison between the simulation and measured results validates the equivalent circuit model, coupled bends with a compensation capacitance patch, and analysis approach. This dissertation also investigates the noise reduction in the slot-induced ground bounce noise by using the differential signaling. An efficient 2D FDTD method together with the equivalent circuits for both the differential lines and the slot is established and simulations are performed for a three-layer structure to characterize the ground bounce coupling. A simple model is then proposed to understand how the differential-coupled microstrip lines can help reduce the ground bounce. Different factors that affect the noise reduction are investigated, such as the coupling coefficient, rising time, skew of differential signaling, and structure asymmetry in the slotline. An experiment is setup to demonstrate the noise coupling between signal lines due to the slot-induced ground bounce and how the significant noise reduction is achieved by employing the differential signaling. Finally, the favorable comparison between the simulation and measured results concludes the proposed equivalent circuit model and analysis approach.Abstract (Chinese) i Abstract iii Contents vi List of Tables viii List of Figures ix Chapter 1 Introduction 1 1.1 Research Motivation 1 1.2 Literature Survey 4 1.3 Contributions 6 1.4 Chapter Outlines 8 Chapter 2 Characteristics of Differential Transmission Lines and Discontinuities 11 2.1 Coupled Microstrip/Strip Lines 11 2.2 Differential Signaling 16 2.3 Differential Impedance 19 2.4 Mixed-mode S-parameters 22 2.5 Discontinuities of Differential Transmission Line 26 Chapter 3 Modeling Technology for Differential Discontinuities 37 3.1 Lumped Circuit Models 38 3.2 Lumped Circuit Model Extraction 40 3.2.1 De-embedding Transmission Line Effects 40 3.2.2 Lumped Circuit Model Extracted Method 42 3.3 Distributed Models 45 3.3.1 Distributed Transmission Line Models 46 3.3.2 Finite Difference Time Domain Method 47 3.4 Summary 55 Chapter 4 Transient Analysis for Differential Bend Discontinuities 67 4.1 Circuit Model for Different Bend Discontinuities 67 4.2 Transient Analysis 68 4.3 Analysis for Practical Routing Schemes 70 4.3.1 Dual Back-to-Back Coupled Bends 70 4.3.2 Coupled Bend with Detour 74 4.4 Experimental Validation of Bend Discontinuities Model 74 4.5 Summary 76 Chapter 5 Noise Reduction Using Compensation Capacitance for Differential Bend Discontinuities 89 5.1 Compensation Capacitance 89 5.2 Parallel Patch Capacitance for Noise Reduction 91 5.3 Experimental Validation 94 5.4 Summary 94 Chapter 6 Reduction in Reflections and Ground Bounce for Signal Line through a Split Power Plane Using Differential Microstrip Lines 103 6.1 Theory and Circuit Modeling 104 6.2 Numerical Simulation 107 6.2.1 A simple Example 107 6.2.2 Simple Model for Ground Bounce Reduction 110 6.2.3 Other Parameters Affecting Ground Bounce 111 6.2.4 Ground Bounce Versus Skew 112 6.2.5 Effects of Asymmetry in Slotline Length 113 6.3 Experimental Validation 115 6.4 Summary 117 Chapter 7 Conclusions and Future Works 137 7.1 Conclusions 137 7.2 Future Works 140 References 142 Paper List 15