Design on a Deserializer and the PCS Service Interface Circuit for the 10GBASE-LX4 Ethernet Receiver

隨著網際網路的快速發展與普及，人們對於網路通信頻寬的需求急遽成長，區域網路的頻寬也已在近幾年內跨入百億位元乙太網路的新紀元。在國際電子電機工程師協會所制定的百億位元乙太網路規格中，10GBase-LX4使用低成本的雷射二極體，光二極體及多模或單模光纖作為光通訊的媒介，相信10GBase-LX4的規格將會在下一代乙太網路中扮演主要角色。 在本論文中，依據百億位元乙太網路系統之規格（10GBase-LX4 Ethernet），我們首先設計了一個在接收機端的序列－並列轉換器，作為一個資料型式轉換的介面。當由時脈資料回復電路所得到的一條高速序列資料被輸入後，藉由偵測其同步用字元的出現與否來達成資料的位元組同步，並將資料轉換為較低速的並列輸出。 此外，在收發機系統中有四條通道，由於通道間特性的不盡相同，造成接收機端四條通道中，信號抵達的時間有快慢差異的不同步現象。我們也設計了一個實體編碼次層的介面電路，此電路將可以校正通道間的時脈資料不同步現象，取得同步之信號，以進一步供上層之媒體存取控制層（MAC）電路作處理。With the fast proliferation and development of the Internet, the demand for high-speed communication network has grown progressively. The bandwidth of local area network (LAN) already enters the generation of the 10 Gigabit Ethernet recently. In the standard of IEEE 802.3ae, which is defined for the 10 Gigabit Ethernet, 10Gbase-LX4 specification utilizes low-cost laser diodes, optical diodes, and multi-mode or single-mode fibers. 10GBase-LX4 will play an important role in the Ethernet in the near future. In this thesis, first we design a deserializer for 10GBase-LX4 receiver. The deserializer functions as a data type converter. As a high speed data stream came from Clock/Data Recovery is input, the deserializer not only achieves byte-level synchronization by detecting the alignment character, but it also converts the high-speed input stream into lower-speed parallel output. Meanwhile, there are four independent lanes in a 10GBase-LX4 transceiver. Due to the imperfectness of each lane, the data skew between lanes will be observed at the receiver. Thus we design a physical coding sublayer (PCS) interface circuit that achieves multi-lane word alignment and provides the required data pattern to the following Media Access Control (MAC) layer for further processing.CHAPTER 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 2 CHAPTER 2 Ethernet Technology Overview 3 2.1 Brief History of Ethernet 3 2.2 Traditional Ethernet 4 2.3 Fast Ethernet 5 2.4 Gigabit Ethernet 8 2.5 10 Gigabit Ethernet 11 2.5.1 Port types 12 2.5.2 Layered Architecture 13 2.5.3 XAUI Interface 15 2.5.4 10 Gigabit Ethernet Applications 17 2.6 Low Cost 10 Gigabit Ethernet 20 2.6.1 10GE-LX4 for MMF Type 21 2.6.2 10GE-CX4 for Short Distance Network 22 CHAPTER 3 Design on a Deserializer for 10GE-LX4 Receiver 25 3.1 Motivation 25 3.2 Synchronization Levels 26 3.3 System Architecture of a 10GE-LX4 Receiver 28 3.4 Circuit Implementation on a Deserializer 30 3.4.1 Circuit Level Architecture 31 3.4.2 DFF and Logic Gates 34 3.4.3 Comma Detector 35 3.4.4 Frequency Divider 37 3.4.5 Phase Selection Circuit 38 3.4.6 Overall Function of the Deserializer 42 3.4.7 Simulated Performance Summary 44 3.4.8 Chip Layout 44 CHAPTER 4 PCS Service Interface Circuit Design 47 4.1 PCS Service Interface (XGMII) 47 4. 2 Multi-Lane Alignment Problem 49 4.3 Related Design of Multi-lane Alignment 51 4.4 Proposed Multi-lane Alignment Architecture 54 4.4.1 System Architecture 54 4.4.2 Alignment Word Detector 57 4.4.3 Loadable Read Pointers Generator 59 4.4.4 System Architecture Optimization 60 4.5 Chip Implementation 61 4.5.1 Simulation Result 63 CHAPTER 5 Conclusion 65 Bibliography 6