Self-Testing and Self-Calibration Technique for Digital to Analog Converter

無論在信號處理或是通訊應用，數位類比轉換器一直是一個無法取代的關鍵元件。其設計上主要的困難在於無法避免的製程漂移問題，如橫跨整片晶圓的梯度、電晶體大小隨機不對稱的與熱電壓變動等影響之下，仍然必須達到所需的高解析度。 長久以來，許多電路佈局的技巧被發展來對抗製程變異，以達到更高的解析度上限。但是這些技巧必須將電流源分割成細小的陣列並牽涉到複雜的繞線，不但增加了寄生電容，也限制了電路的動態表現。而且在設計階段時，無法肯定的預知最後達成的解析度，只能靠不斷的嘗試錯誤與設計更改來達到預定規格。 於是有了自我修正技術的發展，有些技術使用一個外加的慢速，但有較高解析度的內建測試元件(類比數位轉換器或數位類比轉換器)去測試有較低解析度，但操作頻率較高的待測元件。這種方法雖然可行，但是內建一個解析度更高的元件，並不適用於所有的應用。 其他自我修正技術，譬如使用一個參考電流源並在每一個電流源外加一個運算放大器去持續充電並鎖住電流源的閘極偏壓，使每個電流源都和參考電流源一致。但這個方法容易受每個運算放大器間的輸入點偏移影響，只要每個電流源被鎖住的閘極電壓間有微小的不同，將造成電流源之間的電流更大的差異。也有使用熔絲陣列在最後測試時依據測試結果去燒斷適當數量的熔絲來矯正線性度，這個方法雖然能確實確保最後的解析度，但所需的熔絲陣列和外部測試機台都提高了測試成本。 在本論文中，我們提出了一個方法只使用了非常小的額外面積，並且十分容易設計的自我測試與自我修正方法。我們複製了一組原數位類比轉換器的較低位元，搭配一組額外的輸出通道和一個比較器，便可達成自我測試與自我補償。我們使用TSMC 0.35 μm製程設計並且實做了一個14-bit解析度的原型晶片，這個實驗結果顯示我們提出的方法僅用了非常少的額外面積和較短的設計時程，卻能大大的提升數位類比轉換器的解析度。The digital to analog converter (DAC) is a key component in signal processing and telecommunication applications. One major design challenge is to achieve high static and dynamic linearity in the existence of inevitable process variations, e.g., the systematic Vth gradient across the wafer or the random device mismatch. Various layout techniques have been developed to enhance the achievable resolution by canceling out the process variation gradient. However, both the required large current source array and the complex routing introduce parasitic capacitance that poses negative impact on the dynamic performance. Furthermore, the final resolution is not predictable during the design phase and could just try-and-error to tune-up the resolution to meet the specification. Calibration techniques that intend to enhance the DAC resolution have been reported. Some works require an extra built-in high resolution converter (DAC or ADC) as the embedded tester and thus may not be suitable for some applications. Trimming technique use an operation amplifier (OpAmp) and a reference current source used to continuously charge a capacitor that stores the bias voltage of each current source in background. However, the differences between the OpAmp offset voltages may result in large current mismatch. Fuse array is utilized to adjust the DAC INL during the final test. While guaranteeing the final resolution, it requires large area overhead for the fuse array and an accurate external tester, which raises the test cost. The proposed DAC self-testing and self-calibration technique aims at reducing the induced area overhead and the required design efforts. In our technique, the lower significant bits are duplicated. Together with an analog comparator, this duplicated sub-DAC supports both self-testing and self-calibration. A prototype 14-bit DAC has been designed and fabricated in TSMC 0.35 µm technology. The results show that the proposed technique is able to greatly improve the DAC’s static and dynamic performance with low area overhead and shortened design routine.Table of Contents 誌謝 I 中文摘要 II Abstract III Table of Contents IV List of Figures VI List of Tables VIII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 2 Chapter 2 Fundamentals of Digital to Analog Converter Design 3 2.1 DAC Operation Principle 3 2.1.1 Resistor Ladder Architecture 3 2.1.2 Current-Steering Architecture 4 2.1.3 Segmented Architecture 6 2.2 DAC Performance Metrics 6 2.2.1 Static Performance Index 6 2.2.2 Dynamic Performance Index 7 2.2.3 Design of Current Sources 8 2.3 DAC Testing 10 Chapter 3 Testing and Calibration of Digital to Analog Converter__11 3.1 Introduction 11 3.2 Testing of Digital to Analog Converter 11 3.2.1 On-Chip Testing DAC using static parameters 11 3.2.2 Ramp Tracking Technique 12 3.2.3 Dithering Technique 13 3.3 DAC Calibration Techniques 15 3.3.1 Calibration by off-chip high resolution ADC 15 3.3.2 Current Source Calibration by Ideal reference current 15 3.3.3 Calibration of MSB by skipping forbidden regions 16 Chapter 4 The Proposed Testing and Calibration Scheme________18 4.1 Proposed DAC Architecture 18 4.1.1 Calibration Current Source 18 4.1.2 DAC setup and assumptions 19 4.2 Self-Testing Algorithm 20 4.2.1 L-DAC Testing 21 4.2.2 C-DAC and H-DAC Testing 24 4.3 The Self-Calibration Algorithm 24 4.4 Performance Analyzes and Test Accuracy 26 4.4.1 Calibration Range 26 4.4.2 Testing Time and Memory Usage 26 4.4.3 Impact of Comparator Offset 28 4.4.4 Quantization Error 31 4.4.5 Load Mismatch 32 4.5 Comparison with Previous Works 33 Chapter 5 Implementation and Experiment Result______________34 5.1 Behavior Simulation by Verilog-A 34 5.1.1 Testing and Calibration Process 35 5.2.2 Simulation Result 36 5.2 Implementing Architecture 37 5.2.1 Current Source Array 37 5.2.2 H-DAC Decoder Circuit 38 5.2.3 Low Glitch Current Switching 40 5.2.4 Bias Circuit and Reference Current 41 5.3 Test Setup 43 5.3.1 Circuit Setup 43 5.3.2 NI PXI Mixed Signal Test Station 45 5.4 Experimental Result 46 Chapter 6 Conclusions _______ 48 Bibliography ___4