Low Power Techniques for Phase-Locked Loops

本論文主題在於使用0.35-μm標準互補式金氧半製程，實現一個低耗電的鎖相迴路，主要針對以下主題提出新的方法。降低壓控振盪器及除頻器的功率消耗，降低輸出緩衝器的切換功率消耗，及不需除頻器的鎖相迴路。 首先提出一個鎖相迴路，其中包含相位偵測器、電荷汞及利用電源電壓調節來降低功率消耗的壓控振盪器及除頻器。為了降低輸出緩衝器的動態切換功率消耗,使用了一個電荷回收技術,這個輸出緩衝器每次輸出轉態前會先進入三態(tri-state)模式,並利用此時進行電荷回收的動作。 論文的最後提出了利用隙縫相位偵測技術,來達成不需除頻器的鎖相迴路電路。這個方法能在每個參考周期中只會讓參考輸入相位與壓控振盪器的輸出相位比較一次。而所提出的隙縫相位偵測電路,可以降低由電荷汞的不對稱輸出電流所造成的頻率抖動。The goal of this work is to use a standard 0.35-μm CMOS process to implement the phase-locked loops with low power consumption, and the new methods of these three topics, reducing the power consumption of the VCO and divider, reducing the switching power of the output buffer and a dividerless PLL, are presented. The presented PLL include PFD, charge pump circuit, VCO, and divider, successfully reduces the power consumption on VCO and divider by regulated supply technique and novel schematic. To reduce the dynamic switching power consumption, we propose a new charge recycling buffer. The output transistors of the buffer will enter tri-state period first every time and do charge recycling in this period then the output starts transition. A dividerless PLL can be implemented by Aperture Phase Detection (APD) technique because this method only compares reference and VCO phase ones every reference period. A proposed new APD cell can also reduce the jitter caused by the charge pump mismatch current.1 Introduction 1 1.1 Thesis Overview……................................................................................ 2 2 Fundamentals of Phase-Locked Loops 4 2.1 Introduction……........................................................................................ 4 2.2 Fundamentals of PLL……………………………………………………. 6 2.2.1 Voltage Controlled Oscillator…………….................................... 6 2.2.2 Phase Frequency Detector ……………………………………… 7 2.2.3 Charge Pump……………..……………………………………... 9 2.3 Closed-Loop Analysis…………………………………………………… 11 3 Low Power Phase-locked Loop Design and Implement 17 3.1 Architecture………..…….......................................................................... 17 3.2 Building Blocks………..………………………………………………... 18 3.2.1 VCO………………………………………………………………. 18 3.2.1.1 Regulated Supply………………………………………… 20 3.2.1.2 Delay Stage………………………………………………. 23 3.2.1.3 Level Shifter……………………………………………… 28 3.2.2 Divider…………………………………………………………... 29 3.2.2.1 CPL Type DFF……………………………..……………..... 30 3.2.2.2 Frequency Tracking………………………………..……...... 33 3.2.2.3 Regulated Supply Divider and Level Shift…………………. 34 3.3 Experimental Results…………………………………………………... 36 3.3.1 Input/output Interface and Test Setup…………...………………. 37 3.3.2 Experimental Results……………………………………………. 40 3.4 Summary……………………………………………………………….. 44 4 Charge Recycling Buffer 45 4.1 Low Power Output buffer Techniques……............................................... 45 4.2 Charge Recycling Technique……………………………………….…… 48 4.3 Experimental Results……………………………………………………. 59 5 Aperture Phase Detection 63 5.1 Loop Theory………………....……………….......................................... 63 5.2 Shifted-Averaging VCO………..………………………………..……… 67 5.3 Characteristic and Implement of APD………………………………….. 69 5.4 Experimental Results………………………………………………….… 82 5.5 Summary……………………………………………………………….... 87 6 Conclusion 91 Bibliography 9