10 Bit 250MSample/s Interpolation Digital to Analog Converter

現今無線通訊設備之需求嚴苛。而大部分之訊號皆可在數位電路上完成，但資訊需轉換成類比訊號，因此較難建立的部分在於類比-數位轉換器及數位-類比轉換器。 在這篇論文裡，描述用於802.11a之10位元250MSample/s current-steering數位-類比轉換器，並加上內插功能於頻率應用上。對於802.11a發射機之規格而言，頻道之頻寬是20MHz。因此數位-類比轉換器之輸入頻寬被訂於20MHz。用於調變之64 QAM須使用8~10位元。所以，輸入位元數可訂於10位元來增加解析度。 採用內插功能是使濾波器規格之訂定較為寬鬆。而特殊之佈局技術及交換式電流源電路可改善電流源矩陣之效能及尺寸。使用防突波電路是要消除數位資料分同步效應。為了增加數位-類比轉換器之精確度，非線性與線性之效應可被預估在晶片下線之前。 內插式數位-類比轉換器使用Mix Mode 0.35μm CMOS技術且功率消耗60.2mW。顆粒面積為2.25mm2。The requirements on today’s wireless communications equipment are very hard. Most of the signal processing is done in the digital domain, but the information has to be transferred with analog signals, and therefore analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are crucial building blocks. In this thesis, a 10-bit 250MSample/s current-steering DAC is presented for 802.11a transceiver, with interpolation function for frequency domain applications. For 802.11a transceiver standard, the channel bandwidth is 20MHz. Thus the input bandwidth of DAC can be defined 20MHz. 64 QAM which be used modulation has to need 8~10 bit. So, the input bit number is defined 10 bit to increate the resolution. Using interpolation function is to release the specification of filter in the transceiver. The special technique of layout and circuit of switch current source are employed to improve the performances and size of the current source matrix. Deglitch circuit is used to eliminate the digital data asynchronous effects. In order to increate accuracy of the DAC, nonlinearity and linearity effects can be estimated before to tape out the chip. This interpolation DAC uses mix mode 0.35μm CMOS technology and power consumption is 60.2mW. The die area is 2.25mm2.Chapter 1 Introduction 1 1.1 Motivation ………………………………………………1 1.2 Organization ……………………………………………2 Chapter 2 Architectures of DAC 3 2.1 Fundamentals ……………………………………………3 2.2 Quantization ……………………………………………4 2.3 Static Performance ……………………………………6 2.4 Dynamic Performance……………………………………7 2.5 Frequency Domain Performance………………………11 2.6 Performance Limitations ……………………………12 2.7 Voltage Division Architecture ……………………14 2.8 Current Division Architecture ……………………18 2.9 Charge Division Architecture………………………22 2.10 Resistor Based Architecture ………………………28 Chapter 3 Estimation of Performance in Current-Steering DAC 32 3.1 Major Error Sources in Current-steering DACs…32 3.2 Output Resistance Variation for SNDR……………33 3.3 Current Source Mismatch ……………………………34 3.4 Influence of Circuit Noise…………………………36 3.5 INL_yield Estimation in Current-Steering DAC…38 Chapter 4 Design of Interpolation DAC 46 4.1 Oversampling and Interpolation for DAC…………46 4.2 Architecture of Interpolation DAC ………………48 4.3 Preamp circuit and TSPC DFF ………………………49 4.4 Digital circuit and Deglitching circuit ………52 4.5 Implementation of Switch Current Cell …………53 4.6 Output Circuit…………………………………………58 4.7 Layout and Post Simulation…………………………59 4.8 Measured Results………………………………………64 4.9 Conclusionsv……………………………………………71 References 7