Design and Implementation of Clock and Data Recovery Circuit

隨著對傳輸速率需求的不斷提昇，廣域網路以及骨幹網路的串列資列通訊已經演進到了每秒百億位元的等級。光通訊系統將會是未來的主流，乙太網路在此高速網路中扮演相當重要的角色，其中又以時脈與資料回脈系統為最錯綜複雜的零件。由於低成本、低功率及高整合度的優勢，我們使用TSMC.018μm 1P6M CMOS 製程來實現此高速電路。 本論文主要著重在OC-192系統底下的時脈與資料回復系統的設計，我們設計了一個新的壓控振盪器能降低相位雜訊，對整體電路的抖動有更好的改善。在使用長度為二的十五次方減一的PRBS輸入下，鎖定後的回復輸出時脈具有峰對峰1.65ps的抖動。使用1.8伏的電源，整個時脈與資料回復電路有105mW功率消耗。晶片面積則為0.75mm x 0.75mm。With the growing demand on transmission rate, the serial data communication has evolved into tens of gigabits per second for wide area network and the backbones. Optical communication system will be a mainstream in the future, and Ethernet plays an important role in such high speed network. Clock and data recovery circuit (CDR) is the most complicated component of it. We use TSMC 0.18μm 1P6M CMOS technology to implement this high speed circuit to achieve low cost, low power consumption, and highly integrated capability. This thesis focuses on the design of clock and data recovery circuit in OC-192 system. We design a new voltage controlled oscillator which can reduce phase noise, and make better jitter performance of whole circuit. The recovery clock exhibits a peak to peak jitter of 1.65ps for a PRBS sequence of length 215-1. The CDR circuit dissipates a total power of 105mW with a 1.8V supply and occupies a die area of 0.75 mm x 0.75 mm.TABLE OF CONTENTS ABSTRACT i LIST OF FIGURES v CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Overviews of the Thesis 2 CHAPTER 2 CDR IN OPTICAL COMMUNICATION SYSTEMS 5 2.1 Optical Communication System 5 2.1.1 Transmitter Block 6 2.1.2 Receiver Block 8 2.2 System Specifications 9 2.2.1 Jitter Generation 9 2.2.2 Jitter Tolerance 9 2.2.3 Jitter Transfer 10 2.3 Generic CDR Architecture 11 2.3.1 CDR Architecture 12 2.3.2 Full Rate and Half Rate CDR Architectures 13 2.3.3 Referenceless and Referenced CDR Architectures 15 CHAPTER 3 CDR CIRCUIT DESIGN 23 3.1 Clock and Data Recovery Building Block 23 3.1.1 Phase Detector 23 3.1.2 Frequency Detectort 26 3.1.3 Voltage Controlled Oscillator 28 3.2 Behavior Modeling of CDR Blocks 29 3.2.1 The Proposed CDR Architecture 29 3.2.2 Mathematical Model of Bang-Bang PD 31 3.2.3 Design of Loop Parameters 32 CHAPTER 4 BLOCKS OF CDR CIRCUIT DESIGN 35 4.1 Phase Detector and Voltage to Current Converter 35 4.1.1 D Flip-Flop 35 4.1.2 XOR Gate and Voltage to Current Converter 37 4.2 An Improved Voltage Controlled Oscillator 38 4.2.1 Voltage Controlled Oscillator 38 4.2.2 Switching-Capacitor 43 4.2.3 Varactor 43 4.2.4 DC-bias Circuit and VCO Buffer 44 4.3 Loop Filter Parameters Decision 45 4.4 The Simulation Results of Each Building Block 46 CHAPTER 5 IMPLEMENTATION OF THE CDR CIRCUIT 51 5.1 CDR Closed Loop Behavior Simulation in PLL Part 51 5.2 CDR Closed Loop Transistor Level Simulation Results 52 5.3 Chip Layout of the Proposed CDR 55 5.4 Performance Summary 56 CHAPTER 6 CONCLUSION 57 REFERENCE 5