A Low-Voltage CMOS Frequency Synthesizer for UNII-Band Cognitive Radio

隨著無線通訊工業的快速成長，各式各樣無線通訊系統的應用日漸普及。然而頻譜使用情況之量測已證實當今頻譜的使用方式不夠有效率也不具彈性，所以隨著無線網路相關應用持續增加，若是頻譜使用的方式不作適當調整，未來勢必將會面臨到頻譜短缺的窘況。而感知無線電就是被認為能解決上述問題的可能方案。感知無線電的主要精神，就是能隨著外界環境的改變，動態的適當調整其傳輸頻寬、功率、調變方式等而能更有效率的使用頻譜資源。 為了使得無線通訊頻帶的使用更有效率，在本次計劃中是選用國際資訊公用的UNII頻段去建構整個感知無線電系統，設定主要使用者為操作在IEEE 802.11a之通訊協定。此外由於半導體製程愈來愈先進，以及降低系統整合晶片中數位電路的功率消耗之需求，低電壓的設計將勢必獲得設計者的青睞，即使在射頻電路系統中仍有許多挑戰需要被克服以及解決。尤其在頻率合成器的部分，欲將其操作在幾十億赫茲但功率消耗卻只有幾十毫瓦，這在設計上將更為困難。 本篇論文介紹一個應用於感知無線電系統、工作電壓只有1.1伏特的頻率合成器。為了達到低電壓、高速以及高模數的分頻器，這裡利用通過式電晶體邏輯電路(Pass-Transistor Logic)的技巧去降低所需的電壓空間及製程變異。此外可變電容的切換(Varactor-Switching)將被採用在電壓控製振盪器中，目的是為了降低其相位雜訊。整個頻率合成器利用0.18微米互補式金氧半製程已被實現與驗證，其相位雜訊在1MHz的偏差頻率下為-114dBc/Hz，而參考衍生頻率在5MHz的偏差頻率下小於61dBc，整體頻率操作範圍從5.06GHz到6.08GHz之間，而鎖定時間在誤差小於20ppm、從第一個通道到最後一個通道的跳躍範圍下小於40μs。本次實作的頻率合成器在1.1伏的操作電壓下功率消耗為31mW，而其晶片面積為1.3 mm2。With the wireless industry expanding rapidly, various wireless communication systems are emerging. However, the use of spectrum has been demonstrated to be neither efficient nor flexible in the operating band. As more and more wireless applications developing, the available spectrum will soon be depleted if the usage of spectrum is inefficient. Cognitive Radio is thought as a possible solution for this kind of problem. It can sense the surrounding changes and adjust the transmission parameters such as bandwidth, power and modulation properly to obtain better performance and resource utilization. In order to improve the efficiency of radio-frequency band, the project of Cognitive Radio chooses 5GHz UNII band (Unlicensed National Information Infrastructure band) to construct Cognitive Radio system. Here IEEE 802.11a standard is chosen to set up Cognitive Radio system. Besides, due to the technology scaling down and the need to reduce power consumption of digital circuits in mixed-signal systems, the low-voltage design is always attractive despite of many challenges to design RF system. Especially in frequency synthesizer, it is desirable to implement that can operate at multi-GHz in the order of tens of mW. In this thesis, a frequency synthesizer for Cognitive Radio system operating at 1.1V power supply is presented. To achieve low-voltage, high-speed and high-modulus prescaler, a new 32/33 dual-modulus prescaler with pass-transistor logic (PTL) is proposed to reduce the voltage headroom and process variation. In addition, a varactor-switching circuit is used to reduce the phase noise for voltage-controlled oscillator (VCO). The frequency synthesizer has been implemented for verification using 0.18µm CMOS process. The phase noise at a 1MHz offset is -114dBc/Hz and the reference spur at an offset of 5MHz is less than 61dBc. The overall tuning range is between 5.06GHz and 6.08GHz. The settling time within 20ppm from the first channel to the last channel is less than 40µs. The frequency synthesizer dissipates 31mW from a 1.1V supply and occupies a chip area of 1.3mm2.Contents Acknowledgement i Abstract v Contents ix List of Figures xiii List of Tables xvii 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Introduction of Cognitive Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Overview of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2. Fundamentals of Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Key Parameters in Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 Spurious Signals (Spurs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.3 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.4 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 Synthesizer Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 Direct Digital Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . 18 2.3.2 PLL-Based Integer-N Frequency Synthesizer . . . . . . . . . . . . . . . . . 19 2.3.3 PLL-Based Fractional-N Frequency Synthesizer . . . . . . . . . . . . . . 20 2.3.4 Delay-Locked Loop Frequency Synthesizer . . . . . . . . . . . . . . . . . . 21 2.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3. System Analyses and Low-Voltage Considerations . . . . . . . . . . . . . . . . . . . 25 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 System Analyses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.1 Design Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.2 Frequency Synthesizer Architecture . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.3 Linear Model Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.4 Architecture Behavioral Simulation . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 Low-Voltage Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.1 Charge Pump (CP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.2 Voltage-Controlled Oscillator (VCO) . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.3 Frequency Divider (Dual-Modulus Prescaler). . . . . . . . . . . . . . . . . 44 3.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4. Circuit Designs for Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.1 Pulse Swallow Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.2.2 Proposed 32/32 Prescaler with Pass-Transistor Logic. . . . . . . . . . . 57 4.2.2.1 Synchronous Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.2.2.2 Asynchronous Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.2.2.3 Simulation Results and Comparisons. . . . . . . . . . . . . . . . . . 63 4.2.3 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2.4 Simulation Results of Frequency Divider . . . . . . . . . . . . . . . . . . . . 69 4.3 Voltage-Controlled Oscillator (VCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.3.1 Optimization of Passive Components . . . . . . . . . . . . . . . . . . . . . . . 71 4.3.1.1 Inductor Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.1.2 Varactor-Switching Design. . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.2 VCO Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4 Phase Frequency Detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5 Charge Pump (CP) and Loop Filter (LF) . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.6 Closed-Loop Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5. VLSI Implementations and Experimental Results . . . . . . . . . . . . . . . . . . . 87 5.1 Layout Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.2 Testing Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.1 Frequency Tuning Range of VCO . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.3.2 Input Sensitivity of 32/33 Dual-Modulus Prescaler . . . . . . . . . . . . 91 5.3.3 Reference Spur of Frequency Synthesizer . . . . . . . . . . . . . . . . . . . 93 5.3.4 Phase noise of Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . 94 5.3.5 Settling Time of Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . 95 5.4 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10