Digital Signal Processing Engine for Wireless Polar Transmitter Systems

在未來第三代無線通訊需要整合不同調變方式的需求下，發射器在設計上要能夠適用於多模組態的無線傳輸系統並且提供較高的必v。極座標發射器具有合併不同調變方式在高線性度、高必v單一的無線發射器上的能力。在必v的改善方面是使用開關模式的射頻放大器來達成。 在極座標調變方式下，基頻數位信號先從直角座標格式轉換成極座標格式。兩個信號再經由震幅調變器和相位調變器分別做調變，最後在放大器端重新將信號重建回來。在傳統設計上是使用純類比方式來實現此發射器，但隨著CMOS技術不斷的改進，超大型積體電路設計的潮流已逐漸往系統單晶片化為導向。單晶片系統化可以降低實現成本及研發時間。現今通訊系統也已經走向彈性化的設計。而要實現彈性設計必須盡可能在設計初期就必須導入數位信號處理的設計方法來達成。在此我們提出了一適用於極座標發射器系統的數位信號處理引擎，使得在實現上能達到低成本及縮短設計的時間週期。 所提出來的數位訊號處理引擎包含了座標轉換器和數位相位調變器，兩者分別是利用數位座標旋轉器以及數位頻率合成器來實現。此方法在極座標系統下提供了一個具有高度數位整合且無製程漂移影響的電路設計。除此之外此數位訊號處理引擎也擁有快速頻率切換，低相位雜訊及高頻率解析度的特性。我們的設計規格是使用EDGE系統。在系統規格方面，我們會利用不同的模擬來做驗證。 我們採用聯電0.18um 1P6M CMOS製程，設計出來的數位信號處理引擎核心面積約為0.51x0.51mm2而晶片面積則為1.11x1.11 mm2。其數位輸入為5位元的微調頻率控制字，輸出為14位元解析度。最後透過後段晶片模擬來驗證我們的晶片能夠正確的在系統操作頻率26MHz下正常的工作。For third generation (3G) radios with different modulation format, the transmitter needs to provide the capability of multimode wireless transmission and the potential for efficiency gains over the solution based on the conventional transmitter design. Polar transmitter offers the potential of combining different modulation formats with high linearity and high efficiency in a wireless transmitter. Improved efficiency is achieved by employing a switching-mode Radio Frequency (RF) Power Amplifier (PA). In the polar modulation scheme, digital symbols are converted from I/Q format to polar format. Signals are modulated through amplitude modulator and phase modulator respectively then reconstruct at the PA stage. Traditionally, transmitter is realized using pure analog approach. With the rapid advance in CMOS technology, the trend of the VLSI design is then toward System-On-a-Chip (SOC), where design methodology, cost, and turnaround time are major issues. Today’s trend in the wireless communications is toward flexible transmitters. The flexibility is obtained by applying Digital Signal Processing (DSP) methods at as early stage as possible. The proposed DSP engine for the polar transmitter can be implemented with low cost and efficient design periods. Proposed DSP engine consists of rectangular to polar converter and digital phase modulator that are designed based on the COordinate Rational DIgital Computer (CORDIC) and Direct Digital Frequency Synthesizer (DDFS) algorithm respectively. The DSP engine provides a highly integrated solution and no process variations for the polar system. Besides, it also offers fast frequency switching, low phase noise and fine frequency resolution. The proposed DSP engine is designed for the Enhanced Data Rates for Global Evolution (EDGE) system. We also do several kinds of simulations to verify the DSP engine that can meet the EDGE system specification. We have realized the design with UMC 0.18um 1P6M CMOS technology. The core area of the DSP engine is 0.51x0.51mm2 and chip area is 1.11x1.11 mm2. The input word-length is 5-bit with fine-tune frequency control word and output is 14-bit word-length resolution. Finally, the post-layout simulation results show that the chip can operate correctly at the system sampling rate equal to 26MHz.Abstract x Index i List of Figures iii List of Tables v Chapter 1 Introduction 1 1.1 Overview of the Polar System 1 1.2 Proposed DSP Engine for Polar Transmitter 3 1.3 Key DSP Modules in Digital-Based Polar Systems 4 1.3.1 CORDIC 4 1.3.2 DDFS 5 1.4 Motivation and Goal 5 1.5 Thesis Organization 7 Chapter 2 EDGE System 9 2.1 EDGE System Introduction 9 2.2 EDGE Modulation Scheme 10 2.3 System Model Simulation 14 Chapter 3 Rectangular to Polar Converter 17 3.1 Review of CORDIC Algorithm 17 3.1.1 CORDIC with Rotation Mode 17 3.1.2 CORDIC with Vector Mode 18 3.2 Review of CORDIC Architecture Design 19 3.2.1 Iterative Architecture 19 3.2.2 Pipelined Architecture 20 3.3 Design of Rectangular to Polar Converter 21 Chapter 4 Digital Phase Modulator 25 4.1 Review of DDFS Theorem 25 4.2 Symmetric Property of Sine and Cosine 27 4.3 Phase to Amplitude Converter 31 4.3.1 Chebyshev Approximation 31 4.3.2 Taylor Approximation 32 4.3.3 Least Squared Approximation 33 4.4 Noise Analysis 34 4.4.1 SFDR Comparison 36 4.5 Design of Digital Phase Modulator 37 4.5.1 Proposed DDFS architecture 39 Chapter 5 Simulation Results 45 5.1 Simulation Considerations of DSP engine 46 5.2 Simulation Result of DSP Engine 48 5.3 Systems Simulation Result of Polar Transmitter 50 Chapter 6 VLSI implementation of DSP engine 55 6.1 IC design flow 55 6.2 Chip summary 56 6.3 Verification 58 Chapter 7 Conclusions 59 References 6