Design and Implementation of 0.6-V CMOS Analog Circuits

過去十年來，消費性電子市場的快速崛起刺激了可攜式與手持裝置在功能性與降低成本上的發展，然而，這類裝置對電池壽命的要求給電路設計者帶來了新的挑戰，由於電池容量的改良技術發展緩慢，低耗電的電路設計技巧便獲得了大量的關注，此外，考慮電池本身的放電曲線，操作在低供給電壓的電路將有利於更有效的利用電池本身的所有電力，故本篇論文的主題主要關注在適合長時間待機應用的低電壓低功耗類比電路設計，提出三個利用台積電0.18-um CMOS的製程製造的晶片，首先，一個可以產生準確0.6伏電壓的電壓調節器被設計來提供混合訊號電路，透過將電晶體操作在次臨界區與使用低臨界電壓的電晶體，可在僅0.7 伏的輸入電壓下，穩定輸出0.6伏的供給電壓。除此之外，實作了一個操作在0.6伏供給電壓下的Nyquist-Rate模數轉換器，其採用冗餘位元演算法與論文中的電路設計技巧，在低電壓下轉換器產生的非理想效應可以被降低，此轉換器消耗約1微瓦的功率，並且達到6.8個有效位元的效能。最後，本論文提出一個同樣操作在0.6伏供給電壓下的三角積分模數轉換器，透過三角積分的雜訊整形特性，低電壓下面臨的諸多限制將可以被消除，達到了僅約1.5微瓦的功率消耗，並具有57.5 dB的動態範圍。In the past decade, the fast growing market in consumer electronics has motivated the development of portable and hand-held devices with enhanced functionality and reduced fabrication cost. However, the battery lifetime required for the operation of such devices imposes a new challenge on the circuit designer. Provided the moderate advances in battery capacity, design techniques for low-power integrated circuits have attracted great attention. Besides, in consideration of the discharging curve of a battery, low-voltage circuit opera-tions are desirable such that more efficient usage of the battery power can be realized. Therefore, the topic of this thesis is mainly focused on low-voltage and low-power inte-grated circuit designs, and three circuits fabricated by TSMC 0.18-mm CMOS process are presented in this thesis. Firstly, a voltage regulator was designed to generate the supply vol-tage required to power the mixed-signal integrated circuits. By operating the transistors in the subthreshold region, the circuit provides a stable 0.6-V output voltage from an input voltage of 0.7 V. In addition, a Nyquist-rate ADC operating at 0.6-V supply voltage was implemented. By employing the redundant-signed-digit (RSD) algorithm and the proposed circuit technique, the non-ideal effects for low-voltage operations are thus alleviated. With a dc power consumption of 1 uW, the fabricated ADC achieves an ENOB of 6.8 bits. Finally, a 0.6-V Δ-Σ ADC is presented. Through the noise shaping property of Δ-Σ operation, various constraints imposed on the reduced supply voltage are eliminated. The ADC demonstrates a dynamic range of 57.5 dB at a dc power of 1.5 uW.ABSTRACT IX LIST OF FIGURES VIII LIST OF TABLES XV 1 CHAPTER 1: INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 2 2 CHAPTER 2: BACKGROUND 5 2.1 INTRODUCTION TO VOLTAGE REGULATOR 5 2.2 INTRODUCTION TO ADC 6 2.2.1 Introduction 6 2.2.2 General characteristics 7 2.2.3 Static characteristics 7 2.2.4 Dynamic characteristics 8 2.2.5 Nyquist-Rate ADC 9 2.2.6 Oversampling ADC 11 2.3 DESIGN METHODOLOGY 12 2.4 MEASUREMENT METHODOLOGY 13 2.4.1 Battery-Driven Voltage Regulator 13 2.4.2 Auxiliary Circuits for ADC measuring 15 2.4.3 Measurement Setup 16 3 CHAPTER 3: 0.6-V VOLTAGE REGULATOR 19 3.1 INTRODUCTION 19 3.2 BUILDING BLOCKS 20 3.2.1 Voltage Reference 20 3.2.2 Voltage Regulator 21 3.3 EXPERIMENTAL RESULT 22 3.4 CONCLUSION 23 4 CHAPTER 4: ULTRA-LOW-VOLTAGE CYCLIC ADC 25 4.1 INTRODUCTION 25 4.2 ADC ARCHITECTURES 26 4.3 CIRCUIT TECHNIQUES AND BUILDING BLOCKS 28 4.3.1 Low-Voltage Circuit Techniques 28 4.3.2 Sample and Hold 30 4.3.3 Multiplying Digital-to-Analog Converter 31 4.3.4 Operational Amplifier and Comparator 31 4.3.5 Clock Booster and Control Signal 34 4.4 EXPERIMENTAL RESULTS 35 4.5 CONCLUSION 38 5 CHAPTER 5: ULTRA-LOW-VOLTAGE 2ND-ORDER Δ-Σ ADC 39 5.1 INTRODUCTION 39 5.2 ARCHITECTURE 41 5.3 DESIGN TECHNIQUES AND BUILDING BLOCKS 42 5.3.1 Low-Voltage Circuit Technique 42 5.3.2 Current Reference 44 5.3.3 Integrator and Comparator 44 5.3.4 Operational Amplifier 46 5.3.5 Clock, Boostrapped Switch, and Clock Booster 48 5.4 EXPERIMENTAL RESULTS 50 5.5 CONCLUSION 53 6 CHAPTER 6: CONCLUSION 55 6.1 FUTURE WORKS 55 6.1.1 Low-Voltage Ultra-Low Power Pipeline ADC 55 6.1.2 DSP-assistant Analog Circuit Design 55 6.1.3 Higher-Order Δ-Σ ADC with H∞ optimization method on NTF 56 7 BIBLIOGRAPHY 5