A 10-bit 300-Msample/s Pipelined Analog-to-Digital Converter with Open-loop Residue Amplification an Digital Background Calibration

由於積體電路製程進步，電晶體尺寸持續減小，單位面積的數位電路的運算能力也不斷增加。但對於類比電路而言，較低的供給電壓與相對較大的臨界電壓，反而造成了高速電路設計上的困難。類比數位轉換器連結了類比世界與數位電路。由於在他的使用上延伸了純類比信號與類比數位混和信號的運作，類比數位轉換器往往成為了資料運算應用上的瓶頸，限制了整個系統的速度與有效位元數。 在這篇論文中，我們設計了一個輔以數位自動校正之開迴路殘值增益十位元三億赫茲管線式類比數位轉換器。首先經過一個傳統的取樣保持電路。為了數位校正演算法所需，在四位元快閃式類比數位轉換級以及溢位偵測級加上一位元的隨機信號。並且在兩個殘值增益級使用開迴路放大器以減少功率損耗及面積，並且使用固定轉換電導的偏壓電路技術，讓開迴路放大器不因製程與溫度的偏移而受到影響。而開迴路放大器的增益損耗以及非線性失真，均可藉由後端精準的一點五位元類比數位轉換器以及數位自動校正機制成功的去除。By aggressive device scaling in modern integrated circuit technology, the computing ability of digital circuits increases significantly. But the low power supply and relative high threshold voltage of transistors exhibit design difficulties for analog circuit. Analog-to-digital converters provide the link between the analog and digital world. Due to their frequent use of analog and mixed analog-digital operations, A/D converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision. In this thesis, we describe the design and simulation of a 10-bit 300-MSample/s pipelined ADC with open-loop residue amplification and digital self-calibration. First, a traditional sample-and-hold circuit is in front of the ADC. For digital calibration algorithm, 1-bit random number is added to 4-bit flash ADC stage and over-range stage. We employ open-loop amplifiers in two residue amplification stages to save power and area. Using a constant- biasing technique, the open-loop amplifier is process-and-temperature insensitive. The gain error and nonlinearity of open-loop amplifiers are removed by digital calibration algorithm.Table of Contents Table of Contents I List of Figures III List of Tables VII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converter 5 2.1 Introduction 5 2.2 ADC Performance Metrics 5 2.2.1 Signal-to-Noise Ratio (SNR) 5 2.2.2 Signal-to-Noise and Distortion Ratio (SNDR) 7 2.2.3 Effective Number of Bits (ENOB) 7 2.2.4 DNL and INL 8 2.3 Architecture of Analog-to-Digital Converters 9 2.3.1 Flash ADC 9 2.3.2 Two-Step (Semi-Flash) ADC 10 2.3.3 Pipelined ADC 11 2.3.4 Cyclic ADC 12 2.3.5 Summary 12 Chapter 3 The Design of Pipelined Analog-to-Digital Converter 15 3.1 Introduction 15 3.2 Key Building Blocks of Pipelined ADC 15 3.3 S/H Circuit and Conversion Stage Design 19 3.3.1 Switch Technique 19 3.3.2 S/H and MDAC 22 3.4 Low-Power High-Speed Conversion Stage Design 24 3.4.1 Common Source Operation 25 3.4.2 Source Degeneration 29 3.4.3 Constant- Bias 31 3.4.4 Static Comparator 32 3.5 Non-ideality Consideration 33 3.5.1 Open-loop Nonlinearity 33 3.5.2 Closed-loop Nonlinearity 36 3.5.3 Offset Error 37 3.6 Summary 39 Chapter 4 Circuit Implementation and Digital Calibration Technique 41 4.1 Introduction 41 4.2 Sampling Circuit 42 4.3 First-stage Flash ADC and MDAC 45 4.4 Open-loop Residue Amplification 48 4.4.1 Multiply-by-eight Open-loop Amplifier 48 4.4.2 Over-range Stage with Multiply-by-two Open-loop Amplifier 50 4.5 Backend Pipelined ADCs 52 4.6 Digital Calibration 55 4.6.1 Digital Calibration Algorithm 55 4.6.2 Double Digital Calibration Technique 62 Chapter 5 Conclusion 71 5.1 Conclusions 71 Bibliography 7