A Virtual Platform for System-on-Chip Design and Verification

電子系統級(ESL)設計，能夠快速並且及早驗證系統晶片的正確性，對於系統開發人員來說，是個刻不容緩的問題。系統開發人員規劃出整個系統晶片的軟硬體架構之後，必須花費冗長的時間，將硬體開發完成，才能夠開始撰寫軟體，進行模擬與驗證，以確認系統晶片是否可以達到預期的功能。電子系統級(ESL)技術使得系統設計人員可以在架構設計階段，輕易的修改系統架構，進行實驗，收集數據，進而分析與改良系統，亦成了系統晶片架構最早期的可執行規格書。 在本篇論文中，我們提出抽象階層之處理器核心模型，達成在電子系統級(ESL)軟硬體共同模擬與數據分析之能力。我們製作了一組系統晶片虛擬設計平台模擬套件，描述如何運用SystemC語言，發展出高階層指令集模擬器，並達到指令集精準之處理器模型，基於此模型達到高速軟硬共同設計、模擬與驗證;配合抽象階層之系統晶片周邊基礎元件，快速地完成系統晶片平台建置及模擬的工作，來證明它們能確實能帶給系統設計人員一些幫助，並且撰寫應用程式，放入此虛擬之平台中，進行模擬，以驗證系統晶片的設計是否正確無誤與存在於系統規格上之先天障礙。最後我們比較幾個先前的成果，我們所提出的架構可以達到最少五倍的軟硬體共同模擬之速度。Electronic System Level (ESL) design methodology is one approach to tackle the modern System-on-Chip (SoC) design complexity. One major aspect is its capability to develop the system model in higher abstraction level and evaluate the system performance for the later hardware and software partition. It enables the seamless hardware and software development at the same time. In order to ensure a correct hardware and software (HW/SW) co-design, we need to develop a methodology to verify the hardware and software at the same time. Hardware software co-simulation is the most popular approach in HW/SW co-verification. Depending on the design phase, HW/SW co-simulation can be performed at diffident levels of abstraction. In the early design phase, an abstract simulation at the algorithmic or un-partitioned specification level can yield the fastest functional result. However, without the mapping to an architectural executable model (e.g. instruction set architecture), this approach cannot provide reasonable performance estimation of the system. On the other hand, cycle-accurate or nanosecond-accurate model can lead to more accurate timing analysis of the system. However, the corresponding simulation performs so poorly that cannot give the designer any insight into the complete HW/SW interaction. Therefore, we choose the instruction-accurate hardware and software simulation model for the accurate insight to the final system performance. In this thesis, we develop a virtual platform at the instruction-accurate level. This platform is centered by an abstract modeling of an industrial strength ARM-compatible processor, QuteCore. The surrounding modules, such as DMA controller, bus, arbiter, and memory, are also designed in the abstract computational model. Our platform can achieve fast HW/SW co-simulation speed and at the same time record the performance data for the system-level evaluation and design exploration. We demonstrate the effectiveness of our approach with several examples and the results indicate the tremendous value of the abstract processor modeling. Compared to several previous works, our platform can achieve at least 5 times simulation speedup.Acknowledgements..........................................i Abstract.................................................ii List of Figures.........................................vii List of Tables...........................................ix Chapter 1: Introduction...................................1 1.1 Traditional System-Level Design Methodology...........1 1.2 Previous Work HW/SW Co-Simulation.....................2 1.3 Our Instruction-Accurate Virtual Platform.............6 1.4 Organization of the Thesis............................6 Chapter 2: Virtual Platform Overview......................8 2.1 System Architecture...................................8 2.2 System Operation Flow.................................8 2.3 Co-Simulation Method.................................10 Chapter 3: Processor Model...............................14 3.1 QuteCore High Level Overview.........................14 3.2 Instruction Fetch and Exception Handling.............15 3.3 Instruction Execution................................19 3.4 Enhanced User Defined Extension......................24 Chapter 4: Communication Model...........................27 4.1 Bus..................................................28 4.2 Master Interface.....................................33 4.3 Slave Interface......................................34 4.4 Arbiter..............................................36 4.5 Memory Map...........................................38 4.6 Ethernet module......................................40 Chapter 5: Performance Evaluation........................42 5.1 Performance Analysis Manager.........................43 5.2 Performance Result Meter.............................44 Chapter 6: Experimental Results..........................46 6.1 Test Case 1: IDCT Program............................47 6.2 Test Case 2: JPEG Codec..............................51 6.3 Test Case 3: Ethernet Image Transfer.................64 6.4 Simulation Performance...............................65 Chapter 7: Conclusion....................................68 Bibliography.............................................70 Appendices...............................................72 Appendix 1. ARM instruction for architecture version v5TE72 Appendix 2. ARM Addressing Modes.........................73 Appendix 3. User Manual..................................7