Investigation of Strain-Temperature Stress on Rapid Thermal Ultra-thin Gate Oxides

在互補式金氧半導體製程技術上，基礎是建立在金氧半結構，自從金氧半導體場效電晶體發明以來，二氧化矽已經被用以作為其閘極氧化層超過四十年，因為二氧化矽擁有極佳的穩定性與均勻度並且製程簡單。當元件的尺寸為了獲得更佳的密度和性能而縮小時，氧化層的厚度也隨之縮小；然而，隨著製程技術的縮小亦造成更大的功率消耗與封裝密度，因此產生兩個問題需要被考慮，其中一個問題為高溫熱效應在元件性能上的影響，另一個問題為晶圓切割所造成的影響。在互補式金氧半導體製程技術中，應力相關的問題已經成為重要的課題，為數不少的元件由於操作在高溫狀態及在晶圓切割效應下，因而衰退故障。在本篇論文中，我們將致力於應力問題上的研究，用以判斷在熱效應上的改善度；藉由分析金氧半電容結構的電特性來研究矽基板與二氧化矽氧化層系統的應力效應。 在第二章，為了研究熱效應所造成的影響，我們將金氧半電容元件放置於100oC的烤箱內三十秒持續數次，並額外施以不同的外加應力(壓縮及拉伸基板)來觀察其變化；藉由量測電流變化程度和定電壓應力來比較其電特性，實驗結果發現拉伸溫度施壓(tensile-temperature stress)呈現出最好的特性。 此外，在第三章，考慮晶圓切割的影響，我們把晶圓切成條狀並重複之前的實驗程序；我們發現切割確實在金氧半電容元件上造成極大的影響，電流變化程度遠大於未切割之元件；另外，我們觀察到切割過後的元件在經過預先的電性量測，會造成在電流在P型基板的累積區上升，此現象是於未經切割的元件所觀察不到的。The metal-oxide-semiconductor (MOS) structure is the groundwork of complementary metal-oxide-semiconductor (CMOS) technology. Silicon oxide has been used as a gate dielectric of MOSFETs for more than forty years since MOSFET had been introduced due to its excellent stability, uniformity, and easy fabrication process. As the size of device scales down for higher density and performance, the thickness of silicon oxide also scales down. However, as technology downscaling causes greater power and package densities, two issues should be considered. One is the thermal effect on device performance and the other is the influence of wafer-sawing. The stress-related problems have become important issues in the CMOS technology. Many device failures are caused by the stresses at occur during high temperature operations and wafer-sawing. In this thesis we will focus on the study of mechanical stress problems to verify the improvement of thermal effect. We will analyze the electrical characteristics of the MOS structure to study the stress effect on Si/SiO2 system. In chapter 2, we investigated the thermal effect for MOS capacitors after receiving consecutive thermal treatments at 100oC for 30 seconds with various mechanical stresses applied on the substrate. And the measurements of current variation and constant voltage stress (CVS) were made to compare their electrical characteristics. The experimental result shows tensile-temperature stress exhibits the best properties. Furthermore, in chapter 3, for wafer-sawing consideration, we scribed the wafer into the form of a strip and repeated the processes above. We found that scribing result in significant influence on MOS capacitor. The current variations are larger than those without scribing. In addition, we observed that electrical pre-measurement will cause the current level to increase in accumulation region.Chapter 1 Introduction 1 1-1 Motivation of This Work 1 1-2 Equivalent Oxide Thickness (EOT) 2 1-3 Rapid Thermal Processing System 4 1-4 Measurement System 5 Chapter 2 Characteristics of MOS(P) Device under Strain- Temperature Stressing in the form of a Full Wafer 10 2-1 Introduction 10 Saturation gate current for strong inversion MOS capacitor 11 2-2 Experimental 13 2-3 Results and Discussion 14 2-3-1 Changes in Current-Voltage (I-V) Behavior 15 2-3-2 Investigation of Trapping Behavior during Constant Voltage Stress (CVS) 17 2-4 Summary 18 Chapter 3 Characteristics of MOS(P) Device under Strain- Temperature Stressing in the form of a Strip 32 3-1 Introduction 32 Classical Theory of Gate Capacitances in MOS Devices 33 3-2 Experimental 34 3-3 Results and Discussion 35 3-3-1 Changes in Current-Voltage (I-V) behavior 35 3-3-2 Changes in Capacitance-Voltage (C-V) behavior 36 3-3-3 Influence on Electrical Measurement 37 3-3-4 Kinetic Model 38 3-4 Summary 40 Chapter 4 Conclusion and Suggestions for Future Work 56 4-1 Conclusion 56 4-2 Suggestions for Future Work 57 References 5