A 10-bit 250MS/s pipelined ADC

近幾年無線通訊的發展，加速了生活數位化的進展，手機便是一個人手一機的產品，將來手機的趨勢為多功能，旣要可以上網，又要負責家庭安全的監控，也因此無線通訊協定WiMax大量的使用，WiMax需要高速的data rate(80MSPS以上)，這樣的規格需要一個高解析度且高速的類比數位轉換器。 由於低功率為手提式的無線通訊設備很重要的考量，但往往管線式類比/數位轉換器高速但卻要耗大功率，低功率卻沒辦法達到高速，因此要在一定的功率底下達到高速轉換是我們要研究的目標。 線性度為10-bit 速度大於200MS/s的類比數位轉換器常使用管線式類比/數位轉換器。在此希望設計一個操作在1.2V，線性度為10且轉換速度在每秒兩億五千萬次取樣頻率的類比數位轉換器。因此架構採用時間交錯式的管線式類比數位轉換器。 在第一章中，將介紹管線式類比數位轉換器的架構，並討論由電路非線性對轉換器造成的錯誤。在第二章中，時間交錯式的類比數位轉換器及在各通道間不匹配造成的錯誤將被介紹。在第三章中，說明一個新提出提升類比數位轉換器轉換速度的架構，並介紹各個重要電路的設計及模擬結果。第四章是量測的設定及量測結果。在第五章，我們將對這個電路做個總結。In recent years, the improvement in wireless communication equipments speeds up the progress of digital life. Cell phone is an obvious example: everyone has a cell phone. The function of the cell phone tends to be versatile; it is not only used in internet but also used in taking care of home security. Thus, the WiMax protocol in wireless communication is always used. The Wimax needs high speed data rate and a high speed and high resolution ADC is required in the protocol. Due to the portable equipments, low power is an important issue. But it conflicts between high speed and low power. Thus, it is an interesting topic to research in high speed and low power ADC. Pipelined ADC is always used in ADC with resolution larger than 10 bits and speed higher than 200MS/s. We wish to design a 1.2V 10-bit 250MS/s ADC, thus, a time-interleaved pipelined ADC architecture is chosen. Chapter 1 reviews the pipelined ADC architecture and introduces the errors in pipelined ADC. Chapter 2 discusses the time-interleaved ADC and the mismatch effects in time-interleaved ADC. A proposed architecture to increase conversion speed is given in Chapter 3 and the building blocks are also explained. Chapter 4 presents the test setup and measurement result. Final is a conclusion.摘要…………………………………………………………………………………….i Abstract………………………………………………………………………………ii Table of Contents……………………………………………………………………iii List of Figure…………………………………………………………………vi List of table………………………………………………………………….....viii Chapter 1 Pipelined A/D converter.......................…………………………..…1 1.1Motivation……………………………………………………………………1 1.2 Performance metrics……………………………………………………..2 1.2.1 Resolution…..………………………………………………………...2 1.2.2 Accuracy………………………………………………………………...2 1.2.3 Differential Nonlinearity (DNL)………………………………………...2 1.2.4 Integral Nonlinearity (INL)……………………………………………...3 1.2.5 Offset Error………………………………………………………………4 1.2.6 Gain Error………………………………………………………………..4 1.2.7 Signal-to-Noise ratio (SNR)……………………………………………..4 1.2.8 Total Harmonic Distortion (THD)……………………………………….5 1.2.9 Spurious-Free Dynamic Range (SFDR)…………………………………5 1.2.10 Signal-to-Noise and Distortion Ratio (SNDR)…………………………5 1.2.11 Effective Number of Bits (ENOB)……………………………………..6 1.3 Pipelined A/D converter…………………...…………………….…………….6 1.3.1 1.5-bit per stage architecture for 10bit pipelined ADC………………….7 1.4 Error sources in pipelined A/D converter..…………..……………………..….9 1.5 The techniques to cope with the errors in pipelined A/D converter………….12 1.5.1 Capacitor trimming.........................................................................12 1.5.2 Capacitor error average………………………………………………..12 Chapter 2 Time-interleaved Pipelined A/D converter…………………………..19 2.1 Introduction…………………………………………………………………..19 2.2 Time-interleaved ADC……………….………………………………….......19 2.3 Mismatches between channels……………………………………………….20 2.3.1 Offset mismatch effects...…………………………………….21 2.3.2 Gain mismatch effects……….……………………………………..22 2.3.3 Clock timing error effects….………………………………………...23 2.3.4 Combined channel mismatch effects………………………………..24 2.4 The techniques to deal with mismatches in time-interleaved pipelined ADC.. ………………………………………………………………………............26 Chapter 3 Proposed architecture to increase conversion speed ……………………28 3.1 Introduction…………………………………………………………………..28 3.2 The proposed architecture to increase conversion speed…………………28 3.3 High level circuit design…………………………………………………...31 3.4 System simulation………………………………………………………….31 3.5 Integrated circuit design……………………………………………………32 3.5.1 First stage MDAC……………………………………………………...32 3.5.2 Operational amplifier…………………………………………………..34 3.5.3 Comparator…………………………………………………………….35 3.5.3.1 Latch-type comparator…………………………………………...36 3.5.4 Operational amplifier bias circuit and CMFB circuit………………….38 3.5.5 Bootstrap sampling switch…………………………………………….39 3.6 Simulation results……………………………………………………………39 3.6.1 Operational amplifier simulation………………………………………39 3.6.1.1 AC analysis……………………………………………………….39 3.6.1.2 DC analysis………………………………………………………40 3.6.1.3 Transient analysis………………………………………………..41 3.6.1.4 First stage MDAC simulation result summary………………….41 3.6.2 FFT test………………………………………………………………..42 3.6.2.1 Summary of this work………………………………………………43 Chapter 4 Test Setup and Measurement results…………….……………………44 4.1 Introduction………………………………………………………………………44 4.2 Test Setup………………………………………………………………………...44 4.3 Print circuit board design……...…………………………………………………45 4.4 Experimental results……………………………………………………………...48 4.4.1 Static test…………………………………………………………………...50 4.5 Summary…………………………………………………………………………52 Chapter 5 Conclusions…………..………………………………………………..53 5.1 Conclusions…………………………………………………………………53 Bibliography ………………………………………………………………………...5