Implementations of Bus Functional Models for the PCI Express System

現在的電腦系統中時脈一直在提升，但目前電腦系統中常用的匯流排架構，如PCI的匯流排，他的時脈會因為並行的傳輸架構而有所限制。所以PCI-SIG訂出了下一代的IO的傳輸架構的規格稱為PCI Express。而PCI Express是類似於網路架構的分層點對點通訊協定。而他的傳輸效能也大幅的超越現有的PCI架構。而且在軟體介面上它仍是保留了大部分跟PCI相容的設計。所以在未來幾年，我們可以想見的是大量的PCI Express的晶片會被設計採用。 因此為了加速晶片設計的流程，所以本論文提出一系列的匯流排功能性模組的設計。在此論文中我們採用了VERILOG硬體描述語言中的行為性寫法，以及加上驗證語言的擴增(Verification Language Extension)為輔助。實作了這些功能性模組，使其具有PCI Express的完整功能。所以透過它們，我們可以建構各種PCI Express的系統組態。而本文所設計的功能性模組皆可以被控制多項參數，以及可程式化的。所以我們可應用這些模組來建構PCI Express的驗證環境。以協助設計者減少驗證的時程，並增加設計的生產量。With rapid increase in CPU’s speed, inter-chip bus connection becomes the bottlenecks of computing systems. The problem lies on clock skew since the shared bus protocol needs a synchronous clock control. To break the performance limit of PCI/PCI-X, PCI-SIG defines PCI Express, an industry specification for serial connection rather than the original parallel connection. PCI Express is similar to a network protocol. It is a peer to peer, packet based and layered protocol. The PCI Express can provide more bandwidth than PCI/PCI-X bus. Furthermore it is designed to preserve the software/driver interface of earlier PCI version. So in the future, we could see that many chips need to be designed for new applications. To reduce the design schedule of PCI Express system, a set of Bus Function Models (BFM) are provided. In the thesis, we use Verilog with Verification Language Extension (VLE) toolkits to model the behavior of PCI Express elements. All the BFMs contain all the functionalities defined in the specification. Using the BFMs, we could construct all topologies of PCI Express system. The BFMs are also configurable and programmable. So, they could be easily integrated into the system-level verification environment. It could help designers to reduce the time for verification and improve their productivity.List of Tables III List of Figures IV Chapter1. Introduction and Motivation 1 1.1. Proposed Verification Environment with BFMs 2 1.2. Organization of this Thesis 4 Chapter2. Background and Related Work 5 2.1. System Level Verification with BFMs 5 2.2. PCI Express System 6 2.2.1 PCI Express Layering Model 6 2.2.2. PCI Express Fabric Topology 7 2.3. TestWizard Toolkit 9 Chapter3. Layered Functionality of PCI Express System 11 3.1. Transaction Layer 12 3.1.1. TLP Construction and Processing 12 3.1.2. Transaction-Level Mechanisms with Device Resources Management 14 3.1.3. Rules for Ordering and Management of TLPs 16 3.2. Data Link Layer 18 3.2.1. Data Exchange in Link Layer 18 3.2.2. Error Detection and Retry Mechanisms 19 3.2.3. Data Link Control and Management State Machine 20 3.3. Physical Layer 22 3.3.1. Logical Sub-Block 22 Chapter4. Architecture of PCI-Express BFMs 26 4.1. Device Architecture Implementations 26 4.2. Device BFMs 27 4.2.1. Endpoint Model 27 4.2.2. Root Complex Model 28 4.2.3. Switch Model 29 4.2.4. PCI Express to PCI/PCI-X Bridge Model 30 4.3. Software Initialization and Configuration Space 31 4.3.1. PCI-Compatible Configuration Registers 32 4.3.2. PCI Power Management Capability Structure 33 4.3.3. MSI Capability Structure 34 4.3.4. PCI Express Capability Structure 34 4.3.5. Other Parameters for Device Model 37 4.4. Device Programming Interfaces 39 4.4.1. TLP interface 40 4.4.3. DLLP interface 45 4.4.3. PHY Layer Control 48 Chapter5. Experiment Results: Functional Coverage of BFMs 54 5.1. Checklist with Pex_trigger 54 5.2. Functional Coverage 56 Chapter6. Conclusion and Future Works 58 6.1. Conclusion 58 6.2. Future Works 5