Low Power Mapping of Cores onto Hybrid Noc Architectures

隨著系統晶片(System-on-Chip)的發展，越來越多的功能源件被整合在單一晶片中。傳統上，這些元件的資料主要藉由匯流排互相傳遞。然而，當單一系統晶片上的元件個數增加到一定數量時，匯流排系統也將相對變得複雜。這些錯綜複雜的匯流排所造成的影響是大量的功率消耗、傳遞延遲的增加以及訊號同步的困難度上升。晶片網路(Network-on-Chip)是近幾年被提出來解決匯流排問題的通訊架構，在此架構下，各元件之間的資料傳遞將以類似網路的方式進行。儘管有許多晶片網路設計方法一再被提出，而且這些方法也大幅地改善了傳統匯流排所面臨到的問題，然而，一些新的問題也相對地產生。舉例來說，服務品質(QoS)、頻寬最佳化、交換器(switch)設計、網路介面(NI)設計等都是晶片網路所需注意的設計重點。在這篇論文中，我們提出了新的智慧型低功率晶片通訊架構，以解決目前晶片內部資料傳遞所遇到的問題。主要的研究議題有二：一是提出一個結合匯流排及低功率網路架構；二是提出如何在節省功率的前提下將矽智財(Intellectual property)配置於此架構中。With the advance of the semiconductor technology, a huge number of transistors available on a single chip allows designers to integrate tens of intellectual property (IP) blocks together with large amounts of embedded memory. In tradition, data was transferred with bus based on shared medium architectures. However, the bus based on shared medium architectures will not be suitable as they will have to be implemented as hierarchical structures extending to multiple levels. SoC would face the problems like the huge power consumption caused by the complicated bus, the high signal propagation delays which would make synchronous bus based global communication difficult, and also the noise due to the increased RLC effects in deep sub-micro technologies. The NoC (Network-on-Chip) architecture was recently proposed to overcome limitations of the bus architecture. A NoC is an intra-chip communication infrastructure and usually composed by a set of routers inter-connected by point to point communication channels. Even many methods designing the NoC have been proposed which overcome many problems of the SoC, however, there are some new problems emerging. For examples, Quality of Service (QoS), bandwidth optimization, switch design, and Network Interface (NI) design are the points we need to focus on as we design NoC. In this thesis, we discuss two issues, the first one is that we propose a new intelligent architecture combining the SoC and the NoC these two architectures together, and another one is that we propose a solution to the problem of mapping applications onto our architecture while considering execution time and energy consumption.Chapter 1 1 Introduction 1 1.1 Low Power Requirement 1 1.2 Source of Power Consumption in CMOS Cirtuits 2 1.3 System-on-Chip (SoC) 2 1.4 Network-on-Chip (NoC) 3 1.5 Thesis organization 5 Chapter 2 6 Background and Related Work 6 2.1 NoC topology 6 2.2 NoC routing algorithm 12 2.3 Related work 15 Chapter 3 16 Platform Description and Problem definition 16 3.1 Platform description 16 3.1.1 Architecture proposed 16 3.1.2 Energy Model 21 3.1.3 Latency Model 24 3.1.4 Problem definition 25 Chapter 4 28 Proposed method 28 4.1 Procedure of the design 28 4.2 System partition 29 4.3 Mapping 32 4.3.1 Reweighting 32 4.3.2 Add additional nodes 33 4.3.3 Core mapping 33 Chapter 5 39 Experimental results 39 5.1 Experimental results 39 Chapter 6 46 Conclustion 46 Bibliography 4