Multi-Rate LDPC Decoder for IEEE 802.16e

Because of its excellent bit-error-rate performance, the Low-Density Parity- Check (LDPC) Code was adopted in standards of IEEE 802.16e (Metropoli- tan Area Network). The IEEE 802.16e LDPC code currently consists of six di®erent code classes spanning four di®erent code rates (1/2, 2/3, 3/4 and 5/6) and support variable code length. In this thesis, we present a multi- rate LDPC decoder architecture for IEEE 802.16e. Our overlapping schedule can improve the latency of the block-serial layered decoder architecture by 1.7x-2.7x, with a small hardware requirements. The proposed architecture adopts layer decoding algorithm with scaling min-sum approximation and utilizes value-reuse property of min-sum approximation to save memory re- quirement of LDPC decoder. The decoding throughput of the decoder can achieve 500Mbps.Contents 1 Introduction 1 1.1 Low-Density Parity-Check Codes . . . . . . . . . . . . . . . . 2 1.2 Irregualr LDPC Codes . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Structure LDPC Codes . . . . . . . . . . . . . . . . . . . . . . 5 1.3.1 Quasi-cyclic LDPC Codes . . . . . . . . . . . . . . . . 7 1.3.2 LDPC Codes for WiMAX . . . . . . . . . . . . . . . . 8 1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . 13 2 LDPC Decoding Algorithm 14 2.1 LDPC Decoding Algorithm . . . . . . . . . . . . . . . . . . . 14 2.1.1 Sum-Product Algorithm . . . . . . . . . . . . . . . . . 15 2.1.2 Layer Decoding Algorithm . . . . . . . . . . . . . . . . 19 2.2 Min-Sum Apprxoimation . . . . . . . . . . . . . . . . . . . . . 21 2.2.1 Min-Sum . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.2 O®set Min-Sum . . . . . . . . . . . . . . . . . . . . . . 21 2.2.3 Scaling Min-Sum . . . . . . . . . . . . . . . . . . . . . 22 2.2.4 Value-Reuse Property . . . . . . . . . . . . . . . . . . 22 2.3 Software Simulation Results . . . . . . . . . . . . . . . . . . . 23 ii 2.3.1 Double Precision . . . . . . . . . . . . . . . . . . . . . 23 2.3.2 Finite Word Length . . . . . . . . . . . . . . . . . . . . 27 3 Multi-Rate LDPC Decoder Architecture 29 3.1 An Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.1 Channel Information Memory Banks . . . . . . . . . . 31 3.2.2 Check Information Magnitude Memory Banks . . . . . 31 3.2.3 Check Information Sign Bit Memory Bank . . . . . . . 32 3.2.4 Bit Information Memory Bank . . . . . . . . . . . . . . 33 3.2.5 Permutation Rom Bank . . . . . . . . . . . . . . . . . 33 3.2.6 Channel Information Access Order Rom Bank . . . . . 33 3.3 Process Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.1 Rotator . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.2 Get Bit Information Unit Bank . . . . . . . . . . . . . 35 3.3.3 Serial Processing Unit Bank . . . . . . . . . . . . . . . 36 3.3.4 Get Channel Information Unit Bank . . . . . . . . . . 36 3.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4 Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4.1 Original Schedule . . . . . . . . . . . . . . . . . . . . . 39 3.4.2 After Rearrange Memory Access Order . . . . . . . . . 40 4 Implementation Results 47 4.1 Hardware Development Environments . . . . . . . . . . . . . . 47 4.1.1 FPGA Board . . . . . . . . . . . . . . . . . . . . . . . 47 4.1.2 Altra Quarts II . . . . . . . . . . . . . . . . . . . . . . 48 iii 4.1.3 Altera NIOS II . . . . . . . . . . . . . . . . . . . . . . 48 4.2 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3 Veri‾ed Platform . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5 Conclusion and Future Work 57 5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5