Dynamically Reconfigurable Hardware Library based of FPGA

Nowadays when we want to do a design, we need to software-hardware partition first. It is because that we want to put some heavy loading parts of the design into hardware. That would improve the performance of the whole design. Generally if we can put as many functions into hardware as we can, we will get much performance improvement. So, besides the software-hardware partitioning consideration, we need to have a rapidly method to let the Compute Intensive Part (CIP) run in hardware. We propose a Dynamically Reconfigurable Hardware Library (DRHL) method. When we put the CIP into DRHL, we can change to use software Intellectual Property (IP) or hardware IP smoothly. So, we can easily test if our software IP and hardware IP have the same functionality. We also can enhance computation power in System-On-Chip (SOC) with FPGA blocks. Our method provides to reach a better trade-off among flexibility performance and power.Chapter 1.INTRODUCTION 1 1.1 A review of Hardware/Software Codesign 1 1.2 Platform-based Design and IP Reuse 2 1.3 Introduction to dynamically reconfigurable hardware library 3 1.4 Thesis organization 4 2.RELATED WORK 5 3.USING DYNAMICALLY RECONFIGURABLE HARDWARE LIBRARY 7 3.1 The goal of dynamically reconfigurable hardware library 7 3.2 Hardware view of IP 7 3.2.1 Software device driver 9 3.2.2 Interface controller 10 3.2.3 Interface of each IP 12 3.3 Usage of the dynamically reconfigurable hardware library 13 3.3.1 “Search_addr” function 13 3.3.2 “config_logic” function 14 3.3.3 “ip_driver” function 15 3.4 Operation of dynamically reconfigurable hardware library 17 3.5 Add an IP’s effort 17 3.6 The flexibility gain with using this method 19 4.CASE STUDY 20 4.1 Altera ARM Excalibur Development Environments 20 4.2 Porting of real time operating system 23 4.3 Overview of each IP 28 4.3.1 Introduction to JPEG2000 28 4.3.2 AES encoder and DES encoder 31 4.3.2.1 Introduction of DES 31 4.3.2.2 Introduction to AES 33 4.3.3 Introduction to LDPC 36 4.4 Add DWT into DRHL 38 4.5 Experimental result 43 5.CONCLUSIONS AND FUTURE WORK 47 5.1 Conclusions 47 5.2 Future Work 47 REFERENCES 4