A Low power Network-on-Chip Architecture Based on Low Switching Method

低功率超大型積體電路設計是目前最重要的一個議題之一，在晶片系統(System-on-Chip)中，隨著日漸複雜的設計以及IP數目的不斷增加，各IP之間的資料傳遞上成為了一大挑戰，為解決資料傳遞上所產生的問題，目前有許多研究提出以晶片網路(Network-on-Chip)的方式來解決IP之間的資料傳輸問題。在晶片網路架構中，其主要元件為：交換器(Switch)及網路介面(Network Interface, NI)。在本篇論文中，我們提出一個運用在二維網路拓撲(2-D Mesh Topology)上之低傳輸交換編碼的網路介面(Low-Switching Network Interface, LSNI)利用匯流排反向之技術對傳輸資料重新編碼來達到低功率之目的。根據本篇論文實驗結果，當資料傳輸功率占全部功率的80％時，使用本篇所提之方法，平均可節省之功率消耗約20％。本篇研究可有效的減少資料傳輸的交換次數來節省晶片網路的功率消耗。The design of the Low power VLSI circuit is one of the most important issues at the present time technology. In the SoC (System-on-Chip), with ever increasing complexity of VLSI design and IP cores, the inter-communication between IP cores becomes the noteworthy challenge. In order to solve the problem of the data communication, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores. In the NoC, the main components are Switch (or so-called Router) and Network Interface (NI, or so-called Wrapper). In this thesis, we propose a low-switching network interface used in the 2D mesh topology and the bus-invert method, we can accomplish the goal of the low power for recoding the data. According to the experimental results, with the method mentioned in this thesis, the power consumption can be saved about 20% on average when the percentage of the inter-connection power in the total power is 80%. In this work, we can effectively reduce the switching activity of the data transfer to save the power consumption of the NoC data-communication.1 Introduction 1 1.1 The purpose of low power 1 1.2 Power dissipation in CMOS VLSI circuit 2 1.2.1 Dynamic power dissipation 2 1.2.2 Static power dissipation 3 1.3 The concept of the NoC(Network-on-Chip) 4 1.4 Thesis organization 6 2 Related Work 7 2.1 Network protocol of the NoC 7 2.2 NoCs topology 10 2.2.1 Mesh type topologies 10 2.2.2 Tree type topologies 12 2.2.3 Ring type topologies 14 2.3 Routing algorithm 15 2.3.1 XY-routing algorithm 15 2.3.2 DyXY routing algorithm 16 2.3.3 Odd-even turn model 18 2.3.4 West-first routing algorithm 18 2.4 Switching methods 20 2.5 Network Interface 23 3 Proposed Low Power Network-on-Chip Architecture 24 3.1 The motivation and the basic design concept 24 3.2 Proposed Network Interface architecture 24 3.2.1 Bus-invert method 25 3.2.2 The critical problem of previous research 27 3.2.3 Low switching network interface architecture(LSNI) 28 3.3 Packet format 32 3.4 Deadlock problem and our switch architecture 33 4 Experimental Results 38 4.1 Experimental environment 38 4.2 Experimental results 41 5 Conclusion 46 Referenc