Atomic Scale Modeling and Simulation of the Gate Dielectrics (I)

隨金屬氧化半導體技術進步，尺度愈來愈小，使閘極氧化絕緣層的厚度小於2.0-nm，若製程 進入70-nm 則以氧化矽之閘極氧化層的厚度，將無法適用，所以需尋找另一種具有較高介電常 數材料。在分析此材料之性質過程中，傳統積體電路設計和分析應用軟體(如TCAD..等) ，已無 法應付原子尺度問題，所以需要以原子尺度方法，來進行研究。本計畫第一年將以分子動力學模 擬配合古典原子間位勢模式及Tight binding 模式，來研究薄膜層積的問題，由於分子動力學所需 的計算時間較多，需借助平行計算的方法來進行研究，本研究是以個人電腦叢集為架構之平計算 環境。由結果可知;所發展的計算程式碼及計算環境，已可為下一階段利用量子模擬建立基礎。The rapid scaling of -Sbiased CMOS devices has led to silicoino xdide gate insulating film less than 2.-0nm thick. By year 2008, the -7n0m generation needs alternative gate dielectric material with higher K value than that of silicon dioxide. Traditional TCAD tool is not sufficient and atomic scale modeling and simulation is needed for the IC design and analysis. In first year (I), we have carried out the molecular dynamics simulation using empirical interatomic potential and tight binding theory to study the thin-film deposition. PC cluster tool is established for parallel implementation. The results indicate that the computational environment and simulation model and code have been completed and provide the basis for next stage quantum modeling/DFT simulation