硬體描述語言低功率架構設計(3/3)

本計畫的主要目的是在行為層上建立一個低功率電路的合成流程。隨著科技 日新月異，製程已經進步到了奈米的時代，靜態功率消耗也已經變得跟動態 功率消耗一樣地重要。為了管理功率消耗的情形，在這個計畫當中，我們提 出了一個同時考量雙供應電壓與雙臨界電壓的低功率設計方法，來解決行為 層合成的排程問題。當使用我們的方法時，可以獲得一個在功率消耗設計具 有彈性設計空間。我們結合了基因演算法與模擬退火法來解決這樣的排程問 題。實驗的結果證實了約41.6%的功率可以被節省。The goal of this project is to design a synthesis flow for the low power circuit at behavioral level. As the technology scales down to the nanometer dimensions, the static power consumption has become as important as dynamic power consumption. To manage the power consumption, in this project, we propose a low power method, which considers the dual supply voltage (Vdd) and the dual threshold voltage (Vth) at the same time, to deal with the scheduling problem in the behavioral synthesis stage. A flexible design space of power can be achieved when we use the proposed method. A combined algorithm of GA (Genetic Algorithm) and SA (Simulated Annealing) is used to solve the scheduling problem. Experimental results illustrate 41.6% power reduction on average