The study of SOC technology on digital wireless multimedia receiver

積體電路技術在跨入下一世紀前，已進入 0.25 微米CMOS 而向0.18 微米前進，前瞻縮小 的技術使百萬以上電晶體可以做在同一晶片 上， 形成完整系統， 這就是單晶片系統 （System-on-a-chip，SOC）。本研究計畫之目標 對未來3C 之整合及系統晶片（SOC）設計技術 之需求，結合類比、數位電路技巧，及無線通信 傳輸規範配合國科會學門「SOC」規劃，提出一 系列關鍵零組件之電路設計及架構分析。並透過 已可重複使用智產元件（Reusable-IP）之模組管 理形式，作為未來系統晶片成果展示及驗證之實 驗平台。本計畫將進行無線傳輸系統規格擬定及 演算法分析，將分析後的參數作為架構設計的依 據，再由這些參數設計出適合的架構。最後再作 積體電路的製作及驗證、測試。在第一年(88/8/1 - 89/7/31)演算法做完整的資料收集及分析，將整個 系統的系統參數分析出來。Before the advent of next century, the integrated circuit technology has developed into 0.25um CMOS process, and move forward to 0.18um CMOS process. The advanced photolithography technique makes millions of transistors integrated in a single chip, which is called System-on-a-Chip, SOC. The goals of the main program target the integration of 3C and the design techniques of SOC, incorporated with the digital and analog circuit design techniques and wireless-communication transfer protocol cooperating with NSC’s scheme on SOC to propose a series of the circuit designs and architecture analysis of key components. The exhibition and verification platform of the system chip will be based on the module management of the reusable IP. The main program will proceed on the specifications and algorithm analysis of the wireless transfer system; the suitable architecture design will be based on the analyzed parameters; at last, the chip design, verification, and testing will be done. At the first year (88/8/1 – 89/7/31), we made a detailed research on the algorithm, and analyze all parameters needed for the system