Resilient Energy-Constrained Microprocessor Architectures

In the past years, we have seen a tremendous increase in small and battery-powered devices for sensing, wireless communication, data processing, classification, and recognition tasks. Collectively referred to as the Internet of Things (IoT), all these devices have a huge impact on several aspects of our day-to-day life. Since IoT devices need to be portable and lightweight, they depend on battery or environmental harvested-energy as their primary energy source. As a result, IoT devices have to operate on a limited energy envelope in order to increase the supply duration of their energy source. In order to meet the stringent energy-budget of battery-powered IoT devices, extreme-low energy design has become a standard requirement. In this regard, supply voltage downscaling has been used as an effective approach for reducing the energy consumption of Complementary Metal Oxide Semiconductor (CMOS) circuits and enable ultra-low power operation. Although aggressive supply voltage downscaling is a popular approach for extreme-low power operation, it reduces the performance significantly. In this regard, operating in the near-threshold voltage domain (commonly known as NTC) could provide a better trade-off between performance and energy saving, as it can achieve up to 10× energy-saving at the cost of linear performance reduction. However, the broad applicability of NTC is hindered by several barriers, such as the increase in functional failure of memory components, performance variation, and higher sensitivity to variation effects. For NTC processors, wide variation extent and higher functional failure rate pose a daunting challenge to assure timing certainty of logic blocks such as pipeline stages of a processor core and stability of memory elements (caches and registers). Moreover, due to the reduction in noise margin of memory components, susceptibility to runtime reliability issues, such as aging and soft errors, is also increasing with supply voltage downscaling. These challenges limit NTC potentials and force designers to use large timing margins in order to ensure reliable operation of different architectural blocks, which leads to significant overheads. Therefore, analyzing and mitigating variation induced timing failure of pipeline stages and memory failures during early design phases plays a crucial role in the design of resilient and energy-efficient microprocessor architectures. This thesis provides cost-effective cross-layer solutions to improve the resiliency and energy- efficiency of energy-constrained pipelined microprocessors operating in the near-threshold volt- age domain. Different architecture-level solutions for logic and memory components of a pipelined processor are presented in this thesis. The solutions provided in this thesis address the three main NTC challenges, namely increase in sensitivity to process variation, higher memory failure rate, and performance uncertainties. Additionally, this thesis demonstrates how to exploit emerging computing paradigms, such as approximate computing, in order to further improve the energy efficiency of NTC designs