Traditionally, the goal of channel routing algorithms is to route the nets with as few tracks as possible to minimize the chip area and achieve 100 percent connection. However, the manufacturing yield may not reach a satisfactory level if care is not taken to reduce the critical areas which are susceptible to defects. Our approach is to systematically eliminate critical areas by floating, burying, and bumping net segments as well as shifting vias. The yield optimizing routing (YOR) algorithm also minimizes the number of vias since vias in a chip increase the manufacturing complexity which again degrades the yield. The algorithm has been implemented and applied to benchmark routing layouts in the literature. The experimental results show tha...
A parasitic-aware routing optimization and analysis methodology for integrated circuits is developed...
This paper focuses on optimizing and improving time to market of the mixed-signal top-level layout r...
Thesis: S.M., Massachusetts Institute of Technology, Sloan School of Management, Operations Research...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
Ph.D. University of Hawaii at Manoa 2012.Includes bibliographical references.As the minimum feature ...
A new channel routing algorithm called DTR (Defect-Tolerant Routing) is investigated. This algo-rith...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pin...
The impact of spot defects on the susceptibility for electrical failure of a net is analyzed. Based ...
Network-on-Chip technology is gaining wide popularity for the interconnection of an increasing numbe...
[[abstract]]An algorithm known as optimal channel routing (OCR) is proposed which finds an optimal s...
[[abstract]]To successfully route a design, one essential requirement is to allocate sufficient rout...
[[abstract]]An algorithm known as optimal channel routing (OCR) is proposed which finds an optimal s...
Several yield and reliability enhancement techniques have been proposed for the compaction, routing ...
In the design of integrated circuits (ICs), it is important to minimize the number of vias between c...
A parasitic-aware routing optimization and analysis methodology for integrated circuits is developed...
This paper focuses on optimizing and improving time to market of the mixed-signal top-level layout r...
Thesis: S.M., Massachusetts Institute of Technology, Sloan School of Management, Operations Research...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
Ph.D. University of Hawaii at Manoa 2012.Includes bibliographical references.As the minimum feature ...
A new channel routing algorithm called DTR (Defect-Tolerant Routing) is investigated. This algo-rith...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pin...
The impact of spot defects on the susceptibility for electrical failure of a net is analyzed. Based ...
Network-on-Chip technology is gaining wide popularity for the interconnection of an increasing numbe...
[[abstract]]An algorithm known as optimal channel routing (OCR) is proposed which finds an optimal s...
[[abstract]]To successfully route a design, one essential requirement is to allocate sufficient rout...
[[abstract]]An algorithm known as optimal channel routing (OCR) is proposed which finds an optimal s...
Several yield and reliability enhancement techniques have been proposed for the compaction, routing ...
In the design of integrated circuits (ICs), it is important to minimize the number of vias between c...
A parasitic-aware routing optimization and analysis methodology for integrated circuits is developed...
This paper focuses on optimizing and improving time to market of the mixed-signal top-level layout r...
Thesis: S.M., Massachusetts Institute of Technology, Sloan School of Management, Operations Research...