High yield and reliable sorting networks for VLSI and WSI implementations

In this dissertation, a novel approach to on-line error detection and correction for high throughput VLSI sorting arrays is presented first. Two-level pipelining is employed in the design which makes the proposed VLSI sorting array very efficient and suitable for real-time applications. All the checkers are designed as totally self-checking circuits such that the resulting sorting array is extremely reliable. Next, in order to overcome the yield problem in WSI implementations a novel hierarchical modular sorting network is presented. More regularly structured equivalent sorting networks are introduced by replacing shuffle interconnections in the original sorting network with easily reconfigurable interconnections. Redundancy is provided at every level of the hierarchy. Hierarchical reconfiguration is implemented by replacing the defective cells with spare cells at the bottom level first, and goes to the next higher level. Yield analysis is performed to demonstrate the effectiveness of our approach. Efficient implementation of parallel sorting algorithms for mesh-connected processor arrays are also considered in this dissertation. The trapezoid sort which has the properties of very simple control hardware and ease of implementation for mesh-connected processor arrays is developed. Its advantage is that the number of iterations is improved significantly compared with the existing parallel sorting algorithms on mesh-connected processor arrays. Based on this algorithm, an efficient method is proposed to find the median value of the input elements. The elements outside the boundary are excluded from the remaining sorting process to reduce the time complexity. This method is then extended to finding the kth smallest element in the input array. Finally, if the number of elements to be sorted is larger than N, the trapezoid sort algorithm can not be applied directly. Therefore, a modified odd-even merge procedure is presented to merge m sorted input sets. The modified odd-even merge procedure can sort two sets of data inputs concurrently by utilizing the idle processors and then merge them together. A speedup of O(log₂m) over the previous merge-split method is achieved