VLSI REALIZATION OF AHPL DESCRIPTIONS AS STORAGE LOGIC ARRAY.

A methodology for the automatic translation of a Hardware Description Language (HDL) formulation of a VLSI system to a structured array-type of target realization is the subject of this investigation. A particular combination of input HDL and target technology has been implemented as part of the exercise, and a detailed evaluation of the result is presented. The HDL used in the study is AHPL, a synchronous clock-mode language which accepts the description of the hardware at Register Transfer Level. The target technology selected is Storage Logic Array (SLA), an evolution of PLA concept. Use of the SLA has a distinct advantage, notably in the ability to sidestep the interconnection routing problem, an expensive and time-consuming process in normal IC design. Over the past years, an enormous amount of effort has gone into generation of layout from an interconnection list. This conventional approach seems to complicate the placement and routing processes in later stages. In this research project the major emphasis has therefore been on extracting relevant global information from the higher-level description to guide the subsequent placement and routing algorithms. This effectively generates the lower-level layout directly from higher-level description. A special version of AHPL compiler (stage 3) has been developed as part of the project. The SLA data structure formats and the implementation of the Data and Control Sections of the target are described in detail. Also the evaluation and possibilities for future research are discussed