Synchronous fault simulation by surrogate with exceptions.

The contribution of this dissertation is the development of a completely new and accurate algorithm SFSSE for synchronous fault simulation of sequential circuits. The distinctive difference between SFSSE (Synchronous Fault Simulation by Surrogate with Exceptions) and similar approaches for fault simulation in combinational logic circuits is that SFSSE is capable of handling faults stored in more than one memory elements and the reconvergence over time of the stored fault effect with the original fault. The experimental result shows a significant improvement for SFSSE by comparing its execution time to that of parallel fault simulation. After a stored fault list is established during one clock period, all paths from the output of that memory element to the primary outputs might be blocked in subsequent clock periods. A fault is usually propagated through many paths in various subnetworks over several clock periods, and it is detected when only one of these paths reaches a primary output. A new idea for efficiency is suggested in the last chapter to avoid the unproductive simulation activity. In that approach the waste of simulation time is avoided by overlapping the simulation of multiple clock periods