A Low-Power Single-Ended 11-bit SA-ADC with 1 V Supply Voltage and 2 V Input Voltage Range for CMOS Image Sensors

We propose a low-power single-ended 11-bit successive approximation analog-to-digital converter (SA-ADC) for CMOS image sensors. The proposed SA-ADC uses a supply voltage of 1 V instead of 2 V for a 2 V input voltage range in order to reduce power consumption. The proposed ADC reduces the conversion time and area by sampling the input signal only twice and converting it to the most significant bit (MSB) and lower 10-bit without any additional analog circuit. A test chip with the proposed SA-ADC was fabricated using a 0.18 μm CMOS process technology. The measurement results show that the total power consumption of the proposed SA-ADC is 9.0 μW. The static and dynamic power consumptions using a 1 V supply voltage are reduced by 54% and 76%, respectively, compared with those using a 2 V supply voltage. In addition, the proposed SA-ADC achieves a short conversion time of 6.5 μs and occupies a small area of 320 μm × 270 μm. The measured DNL and INL are -0.53/+0.57 LSB and -0.91/+0.71 LSB, respectively.This research was supported by the Industrial and Educational Cooperative R&D Program between Hanyang University and SK Hynix Semiconductor Inc