Charge-sharing read port with bitline pre-charging and sensing scheme for low-power SRAMs

In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre-charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre-charged to full VDD. Read port is designed such that for the read ‘1’ operation, BL shares its charge with BLB, and for read ‘0’ operation, BL is charged toward VDD and BLB is discharged to the ground. The proposed non-VDD BL pre-charging and the charge-sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting preamplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single-ended write driver is also presented that only conditionally charges the write BL. The proposed 10-transistor static random access memory cell using DDR provides more than 2 times read static noise margin, ~72% read power savings, and ~40% write power savings compared with the conventional six-transistor static random access memory. Copyright © 2016 John Wiley & Sons, Ltd.Tools are provided by IC Design Education Center Korea (idec.or.kr). The first and second authors are supported by Higher Education Commission Pakistan (hec.gov.pk). Partial funding for this work was provided by Samsung Electronics Inc. Korea