LDO regulator with high power supply rejection at 10MHz

A new high-frequency power supply rejection (PSR) improvement technique is presented for a low-dropout (LDO) regulator. The proposed technique utilizes a negative capacitance at the gate of the power transistor to enhance the PSR at high frequencies by neutralizing the effect of parasitic capacitances. The simulation results show that the LDO is able to achieve a PSR of -67.9 dB at 10 MHz.This work was supported by the R&D program of MOTIE/KEIT. [10063683, Ultra-precision and ultra-low-power analog circuit IP for smart sensors of mobile devices] and Industrial Core Technology Development Program (10049095, Development of Fusion Power Management Platforms and Solutions for Smart Connected Devices) funded by the Ministry of Trade, Industry and Energy