State encoding of asynchronous controllers is a challenging problem that faces a vast space of solutions. Subtle differences in the insertion of signals may result in significant variations in the complexity of the logic. This paper proposes a novel approach that models the encoding problem as Pseudo-Boolean formula. A cost function that estimates the complexity of the logic is incorporated, where the estimator of essential literals becomes one of the most important terms of the function. The new approach has been tested in 175 benchmarks with encoding conflicts, including 127 four-phase latch controllers. The presence of logic estimators in the formula contributes to an average reduction of 43% in literals when compared to a plain SAT vers...
Since its introduction in 1999, bounded model checking (BMC) has quickly become a serious and indisp...
In this paper we define a new descriptional complexity measure for Deterministic Finite Automata, BC...
as a truth table or a finite state machine state table, where some of the outputs are specified in ...
State encoding of asynchronous controllers is a challenging problem that faces a vast space of solut...
State encoding is one of the fundamental problems in the synthesis of asynchronous controllers. The ...
State encoding is one of the most difficult problems in the synthesis of asynchronous controllers. T...
This paper proposes a state encoding method for asynchronous circuits based on the theory of regions...
State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis m...
Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) in...
This paper proposes a state encoding method for asynchronous circuits based on the theory of regions...
This paper presents an encoding technique that is common for many different logic synthesis problems...
This paper provides a new, generalized approach to the problem of encoding information as vectors of...
When solving a combinatorial problem using propositional satisfiability (SAT), the encoding of the p...
Abstract. This paper presents an encoding technique that is common for many different logic synthesi...
A novel strategy for the logic synthesis of asynchronous control circuits is presented. It is based ...
Since its introduction in 1999, bounded model checking (BMC) has quickly become a serious and indisp...
In this paper we define a new descriptional complexity measure for Deterministic Finite Automata, BC...
as a truth table or a finite state machine state table, where some of the outputs are specified in ...
State encoding of asynchronous controllers is a challenging problem that faces a vast space of solut...
State encoding is one of the fundamental problems in the synthesis of asynchronous controllers. The ...
State encoding is one of the most difficult problems in the synthesis of asynchronous controllers. T...
This paper proposes a state encoding method for asynchronous circuits based on the theory of regions...
State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis m...
Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) in...
This paper proposes a state encoding method for asynchronous circuits based on the theory of regions...
This paper presents an encoding technique that is common for many different logic synthesis problems...
This paper provides a new, generalized approach to the problem of encoding information as vectors of...
When solving a combinatorial problem using propositional satisfiability (SAT), the encoding of the p...
Abstract. This paper presents an encoding technique that is common for many different logic synthesi...
A novel strategy for the logic synthesis of asynchronous control circuits is presented. It is based ...
Since its introduction in 1999, bounded model checking (BMC) has quickly become a serious and indisp...
In this paper we define a new descriptional complexity measure for Deterministic Finite Automata, BC...
as a truth table or a finite state machine state table, where some of the outputs are specified in ...