SIMPAC-T - a simulator for multitransputer systems

Performance evaluation of parallel algorithms and architectures has several advantages. We present an event driven simulator for performance evaluation and modelling of multitransputer systems. The system topology and architectural details are input to the simulator. The application program is mapped by the user on to the system using the higher level primitives of the simulation language provided. The simulator produces performance metrics of resource (processor, communication link) utilization besides process sojourns in various states. A trace file containing the log of the system snapshots is output which can be used for various analyses by the user and the system designer