In this paper, we report a study to understand the fin width dependence on performance, variability and reliability of n-type and p-type triple-gate fin field effect transistors (FinFETs) with high-k dielectric and metal gate. Our results indicate that with decreasing fin width the well-known performance improvement in terms of sub-threshold swing and drain-induced barrier lowering are accompanied by a degradation of the variability and the reliability. As a matter of fact fin width scaling causes (i) higher hot-carrier degradation (HC) in nFinFETs owing to the higher charge carrier temperature for the same internal stress voltages: (ii) worse negative bias temperature instability (NBTI) in pFinFETs due to the increased contribution from th...
The continuous downscaling of CMOS technologies over the last few decades resulted in higher Integra...
The fin-edge roughness and the TiN metal grain work function-induced variability affecting device ch...
Abstract—This paper analyzes the impacts of intrinsic process variations and negative bias temperatu...
The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-e...
High-k metal gate technology improves the performance and reduces the gate leakage current of metal&...
none3noWhile traditional scaling used to be accompanied by an improvement in device performance, thi...
This paper studies the impact of fin width of channel on temperature and electrical characteristics ...
This paper discusses in detail the effects of Sub-10nm fin-width (Wfin) on the analog performance an...
session: nanoelectronic devicesInternational audienceWe expanded our analytical compact model for th...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
This paper studies the impact of fin width of channel on temperature and electrical characteristics ...
The impact of the fin thickness and the gate oxide thickness on the electrical characteristics of Fi...
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and...
We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-...
The continuous downscaling of CMOS technologies over the last few decades resulted in higher Integra...
The fin-edge roughness and the TiN metal grain work function-induced variability affecting device ch...
Abstract—This paper analyzes the impacts of intrinsic process variations and negative bias temperatu...
The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-e...
High-k metal gate technology improves the performance and reduces the gate leakage current of metal&...
none3noWhile traditional scaling used to be accompanied by an improvement in device performance, thi...
This paper studies the impact of fin width of channel on temperature and electrical characteristics ...
This paper discusses in detail the effects of Sub-10nm fin-width (Wfin) on the analog performance an...
session: nanoelectronic devicesInternational audienceWe expanded our analytical compact model for th...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin fie...
This paper studies the impact of fin width of channel on temperature and electrical characteristics ...
The impact of the fin thickness and the gate oxide thickness on the electrical characteristics of Fi...
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and...
We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-...
The continuous downscaling of CMOS technologies over the last few decades resulted in higher Integra...
The fin-edge roughness and the TiN metal grain work function-induced variability affecting device ch...
Abstract—This paper analyzes the impacts of intrinsic process variations and negative bias temperatu...