20-Gbps High-Speed Converged I/O Loop Back Test Design Methodology For Signal Integrity Enhancement

In high-volume manufacturing (HVM), the degradations of signals at high speed and high frequencies will affect test results. In the semiconductor field, inaccuracies of test setup impact a product yield, increase test operating cost and delay products release time. With the demand for rapid improvements in high-speed tests, signal integrity becomes very important. This thesis presents a 20-Gbps high-speed Converged I/O (CIO) and Peripherals Components Interference Express (PCIe) external loop back test design for signal integrity enhancement in a twenty six layer printed circuit board (PCB). The signal integrity effects were studied from the previous PCB design which operates at 5-Gbps at 2.5 GHz maximum operating frequency and the proposed PCB design were evaluated at 20-Gbps at 10 GHz maximum operating frequency. Several key design parameters such as different trace lengths were studied and components that were used in high-speed tests were further investigated from the previous PCB design. These efforts were performed to identify the dominating factors of signal integrity in high-speed test systems. In addition, research studies included the fabrication and measurement of test coupons to understand the impact of design parameters upon the completion of simulation prior to the actual PCB fabrication. In this thesis, the proposed PCB was tested at 20-Gbps and it was capable to operate with an insertion loss (IL) of - 4 dB