Modeling and analysis of cylindrical gate-all around silicon nanowire FET including BOHM quantum potential model

According to Moores’s Law, the number of transistors per square inch on integrated circuits are doubled every year. Now, the transistors size has been scaled down to 15nm. The smaller the transistors size gives more space for transistors to be added in system on chip (SoC) thus will provide a lot of functionality. This can be fundamentally viewed as mechanism leads to deviation of the functional behavior from its ideal case. However, the reduction of channel length into nanometer regime would cause short channel effects (SCEs). New transistor device architecture such as gate-all-around silicon nanowire (GAASiNW) field-effect-transistor (FET) is believed to be a promising future device to solve the scaling problem especially SCEs. GAASiNW is proved to be more immune to SCEs compared to conventional FET. Due to continuous device scaling, quantum effects cannot be neglected especially with today’s technology has reaching 10nm technology node. It has been pointed out by previous researchers that quantum effect such as tunneling effect has become one of the fundamental limitation to accurately describe the charge distribution in GAA SiNW. In this research project, an analytic carrier models in conducting channel for improving electrical characteristic of GAASiNW is investigated. One major focus of this study is to enhance fundamental understanding of quantum effect in an optimized GAASiNW FET device by investigating in details how these quantum effects influence device’s electrical characteristics. The study of quantum effect and comparison between quantum models on GAASiNW FET are compared. The study are conducted by using 3-D TCAD tools. The analytic drift-diffusion including Bohm quantum potential (BQP) model are carried out as its device carrier transport. It is proved that the proposed GAASiNW device with BQP model as the carrier transport able to reduce the DIBL by 83% when applying a low doped at S/D region. In fact, the proposed GAASiNW FET model with BQP model shows a good electrical characteristic when the channel length is scaled to 20 and 16nm