Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation

The 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 26-29 May 2019This work is aimed at the development of a pathbased approach to Statistical Static Timing Analysis. Timing Analysis is an absolutely essential step in the verification of Very Large Scale Integration (VLSI) designs. We propose a novel analytical methodology for the fast calculations of VLSI delay. The problem is stated in such a way that becomes equivalent to finding the maximum of a large set of correlated random variables (RVs). For this purpose, a corresponding extension of extreme value theory of weakly-correlated RVs is developed. Results of simulations showing a comparison of our approach with Monte Carlo simulations are presented. Possible applications, extensions of our methodology and future steps are discussed