Semianalytical model for high speed analysis of all-digital PLL clock-generating networks

The 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, United States of America, 28-31 May 2017In this paper, we propose the model of a network consisting of All-Digital Phase-Locked Loop Network in application to Clock-Generating Systems. The method is based on a solution of a system of non-linear finite-difference stochastic equations and allows us to perform high speed simulations of a distributed Clock Network on arbitrary topology. The result of our analysis show a good agreement with experimental measurements of a 65nm CMOS All-Digital Phase-Locked Loop Network.Science Foundation Irelan