A new ageing-aware approach via path isolation

NBTI is becoming one of the major circuit reliability issues in nano-scale technologies. BTI can cause a threshold voltage shift in CMOS devices and consequently increase circuit delay. This paper proposed a novel ageing aware approach to improve circuit's lifetime. The vulnerable circuit paths against ageing effects are isolated. In addition, minimum area overhead is consumed by adopting proposed synthesis algorithm. The simulation results show that the proposed approach can save up to 67.7% area compared with the conventional over-design technique.