Building ATMR circuits using approximate library and heuristic approaches

Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial hardware replication where designers can explore reduced area overhead combined with some compromise on fault masking. This work presents a novel approach for implementing approximate TMR that combines the approximate gate library (ApxLib) technique with heuristics. The algorithm initially defines the gates to be approximated using testability and observability measures and then chooses the gate transformation based on the bits difference. Experimental results showed good trade-off between the ATMR schemes efficiency in terms of area and fault masking and the computational effort needed to generate them.This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brasil (CAPES) - Finance Code 001 and was also funded by the Spanish Ministry of Economy and Competitiveness and the European Regional Development Fund with the project Evaluación temprana de los efectos de radiación mediante simulación y virtualización. Estrategias de mitigación en arquitecturas de microprocesadores avanzados} (Ref: ESP2015-68245-C4-3-P MINECO/FEDER, UE)