Remote debugging system for FRISC processor implemented in FPGA

Procesor FRISC izveden u programabilnoj logici nadograđen je Control and Debugging Unit modulom za kontrolu i udaljeno ispitivanje stanja procesora. CDU modul implementira slave stranu AXI-lite protokola za komunikaciju posebno dizajniranim automatom stanja, omogućava obradu naredaba za upravljanje radom FRISC-a te dohvat stanja njegovih registara. Udaljeno ispitivanje i upravljanje procesorom ostvaruje se upisivanjem odgovarajućih bitova u upravljački registar CDU modula što je demonstrirano posebno dizajniranom aplikacijom koja parsira naredbe poslane serijskom vezom preko UART-a i pomoću izvedenog sučelja ih prevodi u upravljačke riječi za CDU modul.The FRISC processor, implemented in programmable logic, has been upgraded with the Control and Debugging Unit module for controlling and remote processor debugging. The CDU module implements slave side of the AXI-lite communication protocol with a specially designed state machine, enables processing of FRISC operation management commands and fetching the status of its registers. The remote debugging and processor management is accomplished by entering the corresponding bits into the control register of the CDU module as demonstrated by a specially designed application that parses the commands sent over serial port (UART) and translates them into control words for the CDU module using the derived interface